Wolv Z7 CPU is 6-stage in-order dual issue superscalar processor with floating point unit.
- RV32-IMFDCB
- Fast multiplication unit
- Slow division unit
- FPU with single and double precision
- Fast and slow option for FDIV and FSQRT instruction
- Branch target cache with bimodal branch predictor
- Harvard architecture
- Instruction and Data Tightly Integrated Memory
- UART
- Baudrate 115200
- Start Bit
- Stop Bit
- 8 Data Bits
- No Parity Bit
The installation scripts of necessary tools are located in directory tools. These scripts need root permission in order to install packages and tools for simulation and testcase generation. Please run these scripts in directory tools locally.
- Cloning the repository:
git clone --recurse-submodules https://github.com/taneroksuz/wolv-z7.git
- Execute scripts in directory tools to install necessary tools for compilation and simulation:
cd tools
./riscv.sh
./verilator.sh
- Compile some benchmarks:
make compile
- Compiled executable files are located in riscv and dumped files are located in dump. Select some executable from the directory riscv and copy them into this directory sim/input:
cp riscv/coremark.riscv sim/input/
- Run simulation:
make simulate
- Run simulation with debug feature:
make simulate DUMP=1
- Run simulation with short period of time (e.g 1us, default 10ms):
make simulate MAXTIME=1000
- The simulation results together with debug informations are located in sim/output.
Cycles | Dhrystone/s/MHz | DMIPS/s/MHz | Iteration |
---|---|---|---|
243 | 4113 | 2.34 | 1000 |
Cycles | Iteration/s/MHz | Iteration |
---|---|---|
222723 | 4.49 | 10 |