/* DFSDM Configuration defines */
#define AUDIO_DFSDMx_RIGHT_CHANNEL DFSDM_CHANNEL_2
#define AUDIO_DFSDMx_LEFT_CHANNEL DFSDM_CHANNEL_3
#define AUDIO_DFSDMx_LEFT_FILTER DFSDM1_Filter0
#define AUDIO_DFSDMx_RIGHT_FILTER DFSDM1_Filter1
#define AUDIO_DFSDMx_CLK_ENABLE() __HAL_RCC_DFSDM1_CLK_ENABLE()
#define AUDIO_DFSDMx_CKOUT_PIN GPIO_PIN_3
#define AUDIO_DFSDMx_CKOUT_DMIC_GPIO_PORT GPIOD
#define AUDIO_DFSDMx_CKOUT_AF GPIO_AF3_DFSDM1
#define AUDIO_DFSDMx_CKOUT_DMIC_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
#define AUDIO_DFSDMx_DMIC_DATIN_PIN GPIO_PIN_7
#define AUDIO_DFSDMx_DMIC_DATIN_GPIO_PORT GPIOC
#define AUDIO_DFSDMx_DMIC_DATIN_AF GPIO_AF4_DFSDM1
#define AUDIO_DFSDMx_DMIC_DATIN_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
/* DFSDM DMA Right and Left channels definitions */
#define AUDIO_DFSDMx_DMAx_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
#define AUDIO_DFSDMx_DMAx_LEFT_REQUEST DMA_REQUEST_DFSDM1_FLT0
#define AUDIO_DFSDMx_DMAx_RIGHT_REQUEST DMA_REQUEST_DFSDM1_FLT1
#define AUDIO_DFSDMx_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_WORD
#define AUDIO_DFSDMx_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_WORD
#define AUDIO_DFSDMx_DMAx_LEFT_STREAM DMA2_Stream3
#define AUDIO_DFSDMx_DMAx_LEFT_IRQ DMA2_Stream3_IRQn
#define AUDIO_DFSDMx_DMAx_LEFT_IRQHandler DMA2_Stream3_IRQHandler
#define AUDIO_DFSDMx_DMAx_RIGHT_STREAM DMA2_Stream2
#define AUDIO_DFSDMx_DMAx_RIGHT_IRQ DMA2_Stream2_IRQn
#define AUDIO_DFSDMx_DMAx_RIGHT_IRQHandler DMA2_Stream2_IRQHandler
/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
#define AUDIO_IRQ_PREPRIO ((uint32_t)0x0E)
#include "main.h"
#define SaturaLH(N, L, H) (((N) < (L)) ? (L) : (((N) > (H)) ? (H) : (N)))
/* Private variables ---------------------------------------------------------*/
DFSDM_Channel_HandleTypeDef DfsdmLeftChannelHandle;
DFSDM_Channel_HandleTypeDef DfsdmRightChannelHandle;
DFSDM_Filter_HandleTypeDef DfsdmLeftFilterHandle;
DFSDM_Filter_HandleTypeDef DfsdmRightFilterHandle;
DMA_HandleTypeDef DfsdmLeftDmaHandle;
DMA_HandleTypeDef DfsdmRightDmaHandle;
AUDIO_Drv_t *Audio_Drv = NULL;
WM8994_Init_t codec_init;
/*Buffer location and size should aligned to cache line size (32 bytes) */
ALIGN_32BYTES(int32_t LeftRecBuff[2048]);
ALIGN_32BYTES(int32_t RightRecBuff[2048]);
uint32_t DmaLeftRecHalfBuffCplt = 0;
uint32_t DmaLeftRecBuffCplt = 0;
uint32_t DmaRightRecHalfBuffCplt = 0;
uint32_t DmaRightRecBuffCplt = 0;
static void DFSDM_Init(void)
{
/* Initialize channel 1 (left channel)*/
__HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&DfsdmLeftChannelHandle);
DfsdmLeftChannelHandle.Instance = DFSDM1_Channel3;
DfsdmLeftChannelHandle.Init.OutputClock.Activation = ENABLE;
DfsdmLeftChannelHandle.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
DfsdmLeftChannelHandle.Init.OutputClock.Divider = 24; /* 49.142MHz/24 = 2.047MHz */
DfsdmLeftChannelHandle.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
DfsdmLeftChannelHandle.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; /* N.U. */
DfsdmLeftChannelHandle.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
DfsdmLeftChannelHandle.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
DfsdmLeftChannelHandle.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
DfsdmLeftChannelHandle.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; /* N.U. */
DfsdmLeftChannelHandle.Init.Awd.Oversampling = 10; /* N.U. */
DfsdmLeftChannelHandle.Init.Offset = 0;
DfsdmLeftChannelHandle.Init.RightBitShift = 3;
if (HAL_OK != HAL_DFSDM_ChannelInit(&DfsdmLeftChannelHandle))
{
Error_Handler();
}
/* Initialize channel 0 (right channel)*/
__HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(&DfsdmRightChannelHandle);
DfsdmRightChannelHandle.Instance = DFSDM1_Channel2;
DfsdmRightChannelHandle.Init.OutputClock.Activation = ENABLE;
DfsdmRightChannelHandle.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
DfsdmRightChannelHandle.Init.OutputClock.Divider = 24; /* 49.142MHz/24 = 2.047MHz */
DfsdmRightChannelHandle.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
DfsdmRightChannelHandle.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE; /* N.U. */
DfsdmRightChannelHandle.Init.Input.Pins = DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS;
DfsdmRightChannelHandle.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_FALLING;
DfsdmRightChannelHandle.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
DfsdmRightChannelHandle.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER; /* N.U. */
DfsdmRightChannelHandle.Init.Awd.Oversampling = 10; /* N.U. */
DfsdmRightChannelHandle.Init.Offset = 0;
DfsdmRightChannelHandle.Init.RightBitShift = 3;
if (HAL_OK != HAL_DFSDM_ChannelInit(&DfsdmRightChannelHandle))
{
Error_Handler();
}
/* Initialize filter 0 (left channel) */
__HAL_DFSDM_FILTER_RESET_HANDLE_STATE(&DfsdmLeftFilterHandle);
DfsdmLeftFilterHandle.Instance = DFSDM1_Filter0;
DfsdmLeftFilterHandle.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
DfsdmLeftFilterHandle.Init.RegularParam.FastMode = ENABLE;
DfsdmLeftFilterHandle.Init.RegularParam.DmaMode = ENABLE;
DfsdmLeftFilterHandle.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; /* N.U. */
DfsdmLeftFilterHandle.Init.InjectedParam.ScanMode = ENABLE; /* N.U. */
DfsdmLeftFilterHandle.Init.InjectedParam.DmaMode = DISABLE; /* N.U. */
DfsdmLeftFilterHandle.Init.InjectedParam.ExtTrigger = DFSDM_FILTER_EXT_TRIG_TIM1_TRGO; /* N.U. */
DfsdmLeftFilterHandle.Init.InjectedParam.ExtTriggerEdge = DFSDM_FILTER_EXT_TRIG_RISING_EDGE; /* N.U. */
DfsdmLeftFilterHandle.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER;
DfsdmLeftFilterHandle.Init.FilterParam.Oversampling = 128; /* 49.142MHz/(24*128) = 16KHz */
DfsdmLeftFilterHandle.Init.FilterParam.IntOversampling = 1;
if (HAL_OK != HAL_DFSDM_FilterInit(&DfsdmLeftFilterHandle))
{
Error_Handler();
}
/* Initialize filter 1 (right channel) */
__HAL_DFSDM_FILTER_RESET_HANDLE_STATE(&DfsdmRightFilterHandle);
DfsdmRightFilterHandle.Instance = DFSDM1_Filter1;
DfsdmRightFilterHandle.Init.RegularParam.Trigger = DFSDM_FILTER_SYNC_TRIGGER;
DfsdmRightFilterHandle.Init.RegularParam.FastMode = ENABLE;
DfsdmRightFilterHandle.Init.RegularParam.DmaMode = ENABLE;
DfsdmRightFilterHandle.Init.InjectedParam.Trigger = DFSDM_FILTER_SW_TRIGGER; /* N.U. */
DfsdmRightFilterHandle.Init.InjectedParam.ScanMode = ENABLE; /* N.U. */
DfsdmRightFilterHandle.Init.InjectedParam.DmaMode = DISABLE; /* N.U. */
DfsdmRightFilterHandle.Init.InjectedParam.ExtTrigger = DFSDM_FILTER_EXT_TRIG_TIM1_TRGO; /* N.U. */
DfsdmRightFilterHandle.Init.InjectedParam.ExtTriggerEdge = DFSDM_FILTER_EXT_TRIG_RISING_EDGE; /* N.U. */
DfsdmRightFilterHandle.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC3_ORDER;
DfsdmRightFilterHandle.Init.FilterParam.Oversampling = 128; /* 49.142MHz/(24*128) = 16KHz */
DfsdmRightFilterHandle.Init.FilterParam.IntOversampling = 1;
if (HAL_OK != HAL_DFSDM_FilterInit(&DfsdmRightFilterHandle))
{
Error_Handler();
}
/* Configure regular channel and continuous mode for filter 0 (left channel) */
if (HAL_OK != HAL_DFSDM_FilterConfigRegChannel(&DfsdmLeftFilterHandle, DFSDM_CHANNEL_3, DFSDM_CONTINUOUS_CONV_ON))
{
Error_Handler();
}
/* Configure regular channel and continuous mode for filter 1 (right channel) */
if (HAL_OK != HAL_DFSDM_FilterConfigRegChannel(&DfsdmRightFilterHandle, DFSDM_CHANNEL_2, DFSDM_CONTINUOUS_CONV_ON))
{
Error_Handler();
}
}
/**
* @brief Initialize the DFSDM channel MSP.
* @param hdfsdm_channel : DFSDM channel handle.
* @retval None
*/
static void MX_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable DFSDM clock */
AUDIO_DFSDMx_CLK_ENABLE();
/* Enable GPIO clock */
AUDIO_DFSDMx_DMIC_DATIN_GPIO_CLK_ENABLE();
AUDIO_DFSDMx_CKOUT_DMIC_GPIO_CLK_ENABLE();
/* DFSDM pins configuration: DFSDM_CKOUT, DMIC_DATIN1 pins ------------------*/
GPIO_InitStruct.Pin = AUDIO_DFSDMx_CKOUT_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = AUDIO_DFSDMx_CKOUT_AF;
HAL_GPIO_Init(AUDIO_DFSDMx_CKOUT_DMIC_GPIO_PORT, &GPIO_InitStruct);
/* DFSDM pin configuration: DMIC_DATIN1 pin --------------------------------*/
GPIO_InitStruct.Pin = AUDIO_DFSDMx_DMIC_DATIN_PIN;
GPIO_InitStruct.Alternate = AUDIO_DFSDMx_DMIC_DATIN_AF;
HAL_GPIO_Init(AUDIO_DFSDMx_DMIC_DATIN_GPIO_PORT, &GPIO_InitStruct);
}
/**
* @brief DeInitialize the DFSDM channel MSP.
* @param hdfsdm_channel : DFSDM channel handle.
* @retval None
*/
static void MX_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
{
UNUSED(hdfsdm_channel);
GPIO_InitTypeDef GPIO_InitStruct;
/* DFSDM pin configuration: DMIC_DATIN1 pin --------------------------------*/
GPIO_InitStruct.Pin = AUDIO_DFSDMx_CKOUT_PIN;
HAL_GPIO_DeInit(AUDIO_DFSDMx_CKOUT_DMIC_GPIO_PORT, GPIO_InitStruct.Pin);
GPIO_InitStruct.Pin = AUDIO_DFSDMx_DMIC_DATIN_PIN;
HAL_GPIO_DeInit(AUDIO_DFSDMx_DMIC_DATIN_GPIO_PORT, GPIO_InitStruct.Pin);
}
/**
* @brief Initialize the DFSDM filter MSP.
* @param hdfsdm_filter : DFSDM filter handle.
* @retval None
*/
static void MX_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
/* Enable DFSDM clock */
AUDIO_DFSDMx_CLK_ENABLE();
/* Enable the DMA clock */
AUDIO_DFSDMx_DMAx_CLK_ENABLE();
/*********** Configure DMA stream for LEFT microphone *******************/
DfsdmLeftDmaHandle.Init.Direction = DMA_PERIPH_TO_MEMORY;
DfsdmLeftDmaHandle.Init.PeriphInc = DMA_PINC_DISABLE;
DfsdmLeftDmaHandle.Init.MemInc = DMA_MINC_ENABLE;
DfsdmLeftDmaHandle.Init.PeriphDataAlignment = AUDIO_DFSDMx_DMAx_PERIPH_DATA_SIZE;
DfsdmLeftDmaHandle.Init.MemDataAlignment = AUDIO_DFSDMx_DMAx_MEM_DATA_SIZE;
DfsdmLeftDmaHandle.Init.Mode = DMA_CIRCULAR;
DfsdmLeftDmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
DfsdmLeftDmaHandle.Instance = AUDIO_DFSDMx_DMAx_LEFT_STREAM;
DfsdmLeftDmaHandle.Init.Request = AUDIO_DFSDMx_DMAx_LEFT_REQUEST;
/* Associate the DMA handle */
__HAL_LINKDMA(&DfsdmLeftFilterHandle, hdmaReg, DfsdmLeftDmaHandle);
/* Reset DMA handle state */
__HAL_DMA_RESET_HANDLE_STATE(&DfsdmLeftDmaHandle);
/* Configure the DMA Channel */
HAL_DMA_Init(&DfsdmLeftDmaHandle);
/* DMA IRQ Channel configuration */
HAL_NVIC_SetPriority(AUDIO_DFSDMx_DMAx_LEFT_IRQ, AUDIO_IRQ_PREPRIO, 0);
HAL_NVIC_EnableIRQ(AUDIO_DFSDMx_DMAx_LEFT_IRQ);
/*********** Configure DMA stream for RIGHT microphone ******************/
DfsdmRightDmaHandle.Init.Direction = DMA_PERIPH_TO_MEMORY;
DfsdmRightDmaHandle.Init.PeriphInc = DMA_PINC_DISABLE;
DfsdmRightDmaHandle.Init.MemInc = DMA_MINC_ENABLE;
DfsdmRightDmaHandle.Init.PeriphDataAlignment = AUDIO_DFSDMx_DMAx_PERIPH_DATA_SIZE;
DfsdmRightDmaHandle.Init.MemDataAlignment = AUDIO_DFSDMx_DMAx_MEM_DATA_SIZE;
DfsdmRightDmaHandle.Init.Mode = DMA_CIRCULAR;
DfsdmRightDmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
DfsdmRightDmaHandle.Instance = AUDIO_DFSDMx_DMAx_RIGHT_STREAM;
DfsdmRightDmaHandle.Init.Request = AUDIO_DFSDMx_DMAx_RIGHT_REQUEST;
/* Associate the DMA handle */
__HAL_LINKDMA(&DfsdmRightFilterHandle, hdmaReg, DfsdmRightDmaHandle);
/* Reset DMA handle state */
__HAL_DMA_RESET_HANDLE_STATE(&DfsdmRightDmaHandle);
/* Configure the DMA Channel */
HAL_DMA_Init(&DfsdmRightDmaHandle);
/* DMA IRQ Channel configuration */
HAL_NVIC_SetPriority(AUDIO_DFSDMx_DMAx_RIGHT_IRQ, AUDIO_IRQ_PREPRIO, 0);
HAL_NVIC_EnableIRQ(AUDIO_DFSDMx_DMAx_RIGHT_IRQ);
}
/**
* @brief DeInitialize the DFSDM filter MSP.
* @param hdfsdm_filter : DFSDM filter handle.
* @retval None
*/
static void MX_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
HAL_DMA_DeInit(&DfsdmLeftDmaHandle);
HAL_DMA_DeInit(&DfsdmRightDmaHandle);
}
/**
* @brief Clock Config.
* @param hDfsdmChannel DFSDM Channel Handle
* @param SampleRate Audio frequency to be configured for the DFSDM Channel.
* @note This API is called by BSP_AUDIO_IN_Init()
* Being __weak it can be overwritten by the application
* @retval HAL_status
*/
__weak HAL_StatusTypeDef MX_DFSDM1_ClockConfig(DFSDM_Channel_HandleTypeDef *hDfsdmChannel, uint32_t SampleRate)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hDfsdmChannel);
HAL_StatusTypeDef ret = HAL_OK;
#if 1
RCC_PeriphCLKInitTypeDef rcc_ex_clk_init_struct;
HAL_RCCEx_GetPeriphCLKConfig(&rcc_ex_clk_init_struct);
/* Set the PLL configuration according to the audio frequency */
if ((SampleRate == AUDIO_FREQUENCY_11K) || (SampleRate == AUDIO_FREQUENCY_22K) || (SampleRate == AUDIO_FREQUENCY_44K))
{
/* 429/38 = 11.289 Mhz */
rcc_ex_clk_init_struct.PLL2.PLL2P = 38;
rcc_ex_clk_init_struct.PLL2.PLL2N = 429;
}
else /* AUDIO_FREQUENCY_8K, AUDIO_FREQUENCY_16K, AUDIO_FREQUENCY_32K, AUDIO_FREQUENCY_48K, AUDIO_FREQUENCY_96K */
{
/* 344/7 = 49.142 Mhz */
rcc_ex_clk_init_struct.PLL2.PLL2P = 7;
rcc_ex_clk_init_struct.PLL2.PLL2N = 344;
}
/* Configure prescalers */
rcc_ex_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_SAI1;
rcc_ex_clk_init_struct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2;
rcc_ex_clk_init_struct.PLL2.PLL2Q = 1;
rcc_ex_clk_init_struct.PLL2.PLL2R = 1;
rcc_ex_clk_init_struct.PLL2.PLL2M = 25;
rcc_ex_clk_init_struct.PLL2.PLL2FRACN = 0;
rcc_ex_clk_init_struct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0;
rcc_ex_clk_init_struct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
if (HAL_RCCEx_PeriphCLKConfig(&rcc_ex_clk_init_struct) != HAL_OK)
{
ret = HAL_ERROR;
}
#else
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
/* Configure PLLSAI prescalers */
/* PLL2SAI_VCO: VCO_429M
SAI_CLK(first level) = PLLSAI_VCO/PLLSAIP = 429/38 = 11.289 Mhz */
RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1;
RCC_PeriphCLKInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2;
RCC_PeriphCLKInitStruct.PLL2.PLL2P = 38;
RCC_PeriphCLKInitStruct.PLL2.PLL2Q = 1;
RCC_PeriphCLKInitStruct.PLL2.PLL2R = 1;
RCC_PeriphCLKInitStruct.PLL2.PLL2N = 429;
RCC_PeriphCLKInitStruct.PLL2.PLL2FRACN = 0;
RCC_PeriphCLKInitStruct.PLL2.PLL2M = 25;
RCC_PeriphCLKInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0;
RCC_PeriphCLKInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK)
{
Error_Handler();
}
#endif
return ret;
}
/**
* @brief Half regular conversion complete callback.
* @param hdfsdm_filter : DFSDM filter handle.
* @retval None
*/
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
if (hdfsdm_filter == &DfsdmLeftFilterHandle)
{
DmaLeftRecHalfBuffCplt = 1;
/* Invalidate Data Cache to get the updated content of the SRAM*/
SCB_InvalidateDCache_by_Addr((uint32_t *)&LeftRecBuff[0], sizeof(LeftRecBuff) / 2);
}
else
{
DmaRightRecHalfBuffCplt = 1;
/* Invalidate Data Cache to get the updated content of the SRAM*/
SCB_InvalidateDCache_by_Addr((uint32_t *)&RightRecBuff[0], sizeof(RightRecBuff) / 2);
}
}
/**
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
using HAL_DFSDM_FilterGetRegularValue.
* @param hdfsdm_filter : DFSDM filter handle.
* @retval None
*/
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
{
if (hdfsdm_filter == &DfsdmLeftFilterHandle)
{
DmaLeftRecBuffCplt = 1;
/* Invalidate Data Cache to get the updated content of the SRAM*/
SCB_InvalidateDCache_by_Addr((uint32_t *)&LeftRecBuff[1024], sizeof(LeftRecBuff) / 2);
}
else
{
DmaRightRecBuffCplt = 1;
/* Invalidate Data Cache to get the updated content of the SRAM*/
SCB_InvalidateDCache_by_Addr((uint32_t *)&RightRecBuff[1024], sizeof(RightRecBuff) / 2);
}
}
int Audio_Record_Start(void)
{
/* Start DFSDM conversions */
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&DfsdmRightFilterHandle, RightRecBuff, 2048))
{
printf("HAL_DFSDM_FilterRegularStart_DMA failed!! DfsdmRightFilterHandle\r\n");
return (-1);
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&DfsdmLeftFilterHandle, LeftRecBuff, 2048))
{
printf("HAL_DFSDM_FilterRegularStart_DMA failed!! DfsdmLeftFilterHandle\r\n");
return (-1);
}
return 0;
}
int Audio_Record_Stop(void)
{
MX_DFSDM_ChannelMspDeInit(&DfsdmLeftChannelHandle);
MX_DFSDM_FilterMspDeInit(&DfsdmLeftFilterHandle);
return 0;
}
void Audio_Record_Config(void)
{
MX_DFSDM1_ClockConfig(&DfsdmLeftChannelHandle, 16000U);
MX_DFSDM_FilterMspInit(&DfsdmLeftFilterHandle);
MX_DFSDM_ChannelMspInit(&DfsdmLeftChannelHandle);
DFSDM_Init();
}
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
typedef enum
{
AUDIO_RECORD_MESSAGE_EVENT_PROCESS = 0,
AUDIO_RECORD_MESSAGE_EVENT_STOP
} AudioRecordMessageEventTypeDef;
#define AUDIO_RECORD_MAX_TIME_MS 10000
osMessageQId AudioRecordEvent;
uint32_t AudioRecordCount = 0;
void AudioRecordTick(void)
{
if (AudioRecordCount)
{
AudioRecordCount--;
osMessagePut(AudioRecordEvent, AUDIO_RECORD_MESSAGE_EVENT_STOP, 0);
}
}
void AudioRecordThread(void const *argument)
{
UNUSED(argument);
osEvent event;
printf("AudioRecordThread start ...\r\n");
osMessageQDef(AUDIO_Record_Queue, 10, uint16_t);
AudioRecordEvent = osMessageCreate(osMessageQ(AUDIO_Record_Queue), NULL);
if (0 == AudioRecordEvent)
{
printf("Audio thread osMessageCreate failed\r\n");
Error_Handler();
}
Audio_Record_Config();
Audio_Record_Start();
//AudioRecordCount = AUDIO_RECORD_MAX_TIME_MS;
while (1)
{
event = osMessageGet(AudioRecordEvent, osWaitForever); //osWaitForever
if (event.status == osEventMessage)
{
switch (event.value.v)
{
case AUDIO_RECORD_MESSAGE_EVENT_PROCESS:
printf("AUDIO_RECORD_MESSAGE_EVENT_PROCESS\r\n");
break;
case AUDIO_RECORD_MESSAGE_EVENT_STOP:
Audio_Record_Stop();
break;
default:
break;
}
}
}
}
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