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MD5 core in verilog
Hi, Can you please share some reading material related to MD5 implementation which you referred while its implementation?
I am giving message of around 576 from md5_tb. After 512 bits of message i am making rdy signal low then again once the rdy_o signal is goes high i am giving next 64 bit data along with padding and message
length. in this case i am not getting the correct hash code. what i have observed is msgram0_we goes low
when md5_round == 16 and rrr == 0. so when message is greater than 512 that time for first block when rrr goes high it is not going low for second block of 512 hence rrr goes low on two condition even rst_i goes high or md5_round + 1 == 0(this second condition is not getting true any time). correct me if i am
wrong.
So please check and let me know how to process in md5_tb if msg greater than 512.Thanks in advance.
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