squishy-scsi / hardware Goto Github PK

The single block unit for the SCSI front-end needs to be designed.

Ideally all of the physical bus variants can be supported by a single block, if not design will be altered.

The following items should be completed in the same block in an ideal circumstance.

• HVD Support
• LVD Support
• SE Support

The following updates need to be made to make the rev1 hardware functional.

• Replace Winbond Flash chip with the GD25Q64E
• Replace the 16MHz osc on the ULPI PHY with the proper 13MHz one

The bus for the HyperRAM cache for the FPGA needs to be routed.

Ensure termination, decoupling and length matching are done properly.

The SCSI front-end needs to be able to enable/disable parts of the transceiver in order to allow for the bus to function.

Roughly the groups are:

• Busy Enable
• Select Enable
• Msg/Req Enable
• Transmit Enable
• Atn/Ack Enable

The rev2 hardware has a current/voltage ADC to measure TERMPWR to try to detect if the hardware has a fault.

This ADC as well as the TERMPWR enable/disable circuitry needs to be laid out and hooked up.

The rev2 hardware has support for an external trigger and refclk to assist in the analysis and capture of SCSI traffic.

The two SMA connectors on the left edge of the rev2 board need to be routed and length matched.

The power supply for rev2 needs to be completed.

• 3v3 Rail
• 2v5 Rail
• 1v8 Rail
• 1v2 Rail
• 1v15 Rail

Gateware support for the rev2 hardware external trigger and reference clock needs to be implemented and documented.

The rev2 hardware is designed to have an interchangable bus / device front-end based on using the Samtec QTH-060-01-X-D-RA-PGP as it's connector.

Ideally we will have a board for each of the following SCSI connectors, more than one per board is okay, in the case of the IDC connectors and other small connectors.

• HD50
• DB25
• HD68
• C50
• IDC50
• IDC68
• SCA80
• VHDCI
• MD50
• MD68

The debug/test and programming jig for the rev2 hardware needs to be designed.

This issue is blocked by:

• #13
• #12
• #10
• #9
• #7
• #6
• #4

The rev2 hardware has an on-board micro SD Card slot for storage emulation or other possible features, ideally the communication would be over SDIO if possible, but fallback to SPI mode for the SD Card might be needed.

The layout for the FPGA supervisor mcu needs to be completed.

• Connect SPI bus + control signals to FPGA
• Connect SPI bus to onboard flash
• Connect LEDs
• Connect to DFU trigger button

Route/layout the bus for the SD Card to connect to the FPGA.

The rev2 hardware has a plethora of status LEDs to show the end user its internal state as well as any faults.

This need to be hooked up to the FPGA and the supervisor micro respectively.