RFE: Make switch statement optimized for one-hot encoded arguments about spinalhdl HOT 4 CLOSED

I’d suggest to enter the code like the following. It should be functionally equivalent but points out better the intent.

(* parallel case *)
case(1) // synopsys parallel_case
    ((pc_state & `PcState_defautEncoding_Idle) == `PcState_defaultEncoding_Idle): begin

Also this would allow the code to be used for other *hot encodings as well, e.g. two-hot.

However, the parallel_case tags should only be applied if really all cases have been decoded. Is SpinalHDL already capable of detecting this property in a water-proof way?

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@typingArtist
So you have access to the whole AST durring the Verilog generation.
There is where the switch cases statements is emited :

The is isPure is calculated to be true if only literals are used in the SpinalHDL 'is' statements, as Verilog doesn't support case statements with non literal cases.

So the generation of switch statement with only literal stuff is there

@typingArtist and @tomverbeure
What happend if you throw some

(* parallel case *)
case(1) // synopsys parallel_case
    ((pc_state & `PcState_defautEncoding_Idle) == `PcState_defaultEncoding_Idle): begin

code into non synposys / parrallel cases capable tools ? is that still legal verilog ?

from spinalhdl.

However, the parallel_case tags should only be applied if really all cases have been decoded.

I believe that's only true for full_case, but not for parallel_case. My rule of thumb is to never ever use full_case. It's too dangerous. For parallel_case, the simply rule of them is the one listed above: if you know for sure that the input is one-hot, then you're good, even if you don't cover all the options.

code into non synposys / parrallel cases capable tools ? is that still legal verilog ?

Tools that don't implement the parallel case will implement a priority encoder instead of a flat encoder. But it will functionally still be totally fine. It's legal Verilog.

Tom

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@typingArtist
Your patch is great! As expected, the clock speed of my design went up, and number of gates went down.

I suggest 2 fixed:

• // synopsys parallel_case -> // synthesis parallel_case

  I'm old school, but even if some tools still don't support (* parallel_case *), they all support synthesis instead of synopsys.

• Either keep the (* parallel_case *) attribute, or provide an option to use one or the other or both.

Tom

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