Arbitrary data bundle type for Axi4Stream about spinalhdl HOT 12 OPEN

@KireinaHoro Pused to SpinalHDL dev branch :)

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Hi,
i kinda recentrly implemented a feature a bit like it. But instead of using a DataType parameter, i used something a bit more "dynamic"
it is named HardMap :
https://github.com/SpinalHDL/VexiiRiscv/blob/39ec45a01d0cf9e1701823f64f1897337fdc34f1/src/main/scala/spinal/core/HardMap.scala#L8

Idea is that you can create it and fill it with NamedType a bit like a hash map.

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This looks interesting. So I imagine one would put this into the data element of the Axi4Stream bundle? How would this look like if used in IO?

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Something around that :

  case class MyBus(things : Seq[NamedType[_ <: Data]]) extends Bundle{
    val hm = new HardMap()
    things.foreach(e => hm.add(e))
  }
  
  val CTX_A = NamedType(Bool())
  val CTX_B = NamedType(Bool())
  
  val bus = MyBus(Seq(CTX_A, CTX_B))

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Since Axi4Stream is very much an analog of Stream would it not make sense to make it generic over the type?

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would it not make sense to make it generic over the type?

How do you mean it ? (for me to understand)

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https://fars.ee/Co-Z/scala @Dolu1990 I have something like this that works quite well for my use case. But this is not the same thing as the HardMap solution you proposed since I pass in a payloadType: Bundle to the config.

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How do you mean it ? (for me to understand)

To have the payload as a generic type, just like the Stream has it, i.e.
Axi4Stream(MyBundle(), ...) and maybe a conversion function to Axi4Stream(Bits(), ...) for the edges.
Do we have to stick to the "type" in the spec here?

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since I pass in a payloadType: Bundle to the config.

Yes it is also a good solution, [T <: Data] ... payloadType[HardType[T]]

I'm not sure what is the best between having a ArrayBuffer[NamedType] vs payloadType[HardType[T]]

Maybe i'm bing too much into the HardMap thing because of composability in CPU design, which isn't the rule in general design

Axi4Stream(MyBundle(), ...) and maybe a conversion function to Axi4Stream(Bits(), ...) for the edge

Ahhh i would say it would be kinda too much away from the the Axi4stream spec usage.
Axi4stream is realy a byte oriented stream, with some eventual "compagnions", so more Axi4StreamConfig(dataWidth, ... , optionalHardType)

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@Dolu1990 I'm trying to build something else with the HardMap as the USER field; would you mind upstreaming it into SpinalHDL (from VexiiRiscv)? Thanks :)

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Keep in mind, not sure what is the best overall :

• Bits with parametrable bit count
• Parametrable Data type
• HardMap with elements in parameter

I'm thinking that maybe the best is just Bits, as when you have a Axi4Stream interconnect, you realy don't care about the meaning of the data.

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I agree about the Bits option; we can probably use HardMap to wrap another layer for such a use-case. However, the current implementation enforces a Byte interface as required by the standard; allowing Bits means deviation.

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