RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.

CPU design requires design expertise in several specialties: electronic digital logic, compilers, and operating systems. To cover the costs of such a team, commercial vendors of computer designs, such as ARM Holdings and MIPS Technologies charge royalties for the use of their designs, patents and copyrights. They also often require non-disclosure agreements before releasing documents that describe their designs' detailed advantages. In many cases, they never describe the reasons for their design choices.

RISC-V was started with a goal to make a practical ISA that was open-sourced, usable academically and in any hardware or software design without royalties.

We focus on Developing a RISC-V core which executes the RV32IM (I-Basic Integer Operations, M-Multiplication and Division Operations) Instruction set architecture .The objective is to develop a basic processor that can be further customized to support other RISC-V Extensions (A,C etc). This can also be customized for different applications such as IOT, Embedded Systems and Machine Learning. This is a first step towards understanding the working of a processor along with other Computer Architecture concepts.

The idea is to design a RTL-Level Code of the Core using Vivado design suite and implement the design in a FPGA board for evaluation.The following image describes the different stages of the design Flow

Architecture Type : Harvard Architecture Cycles : Multicycle
ISA : RV32I
Cache : Planned for later stage
Branch Prediction : Planned for later stage
Pipelines : Work in progress

Note : subject to change

• Akil M [https://github.com/akilm]
• Mukesh Gandhi [https://github.com/MukkeshGandhi09]
• Venkatesh T K [https://github.com/VenkateshTK]
• Sudharsan S [https://github.com/sudharsan2000]
• Gaurav Singh [https://github.com/GauravSingh789]
• Kirthika Srinivasan [https://github.com/kirthi-ka]