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42-cursus's Introduction

Makefile

  • set a rule in Makefile
command_echo:
    echo "hello world"
  • Dependency in Makefile
command_dependency: command_echo
    echo "hello world again"
  • variable
TEXT = "test"
command_test:
    echo $(TEXT)
%.o: %.foo
    fooc $(FOOFLAGS) -o $@ -c $<
Then, whenever make needs to build xyzzy.o, and there is a file named xyzzy.foo, it will use that rule to compile it.
all: library.cpp main.cpp
In this case:

$@ evaluates to all
$< evaluates to library.cpp
$^ evaluates to library.cpp main.cpp

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