sneakypete81 / atom-vhdl-entity-converter Goto Github PK

entity test is
generic (
  GENERIC1   : integer;
  GENERIC2   : integer
);
port (
  clk   : in std_logic;
  reset : in std_logic;
  clear : in std_logic
);
end test;

entity my_component is
   port (
      -- System signals
      clk_in               : in  std_logic;  -- 10 MHz clock
      reset_in             : in  std_logic;  -- Syncronous reset

      -- Control port
      cmd_in               : in  std_logic_vector(15 downto 0) ;    -- Command Port
      cmd_valid_in         : in  std_logic;                          -- Command Valid, 1 cycle

      -- Data port
      data                 : out std_logic_vector(15 downto 0) ;    -- Data out Port
      data_valid           : out std_logic;                         -- Data Valid, 5 cycles

      -- Error Signals
      cmd_error            : out std_logic_vector -- Invalid command
   );
end my_component;


my_component_i : my_component
port map(
   -- System signals
   clk_in               => clk_in,     -- 10 MHz clock
   reset_in             => reset_in ,  -- Syncronous reset

   -- Control port
   cmd_in               => cmd_in,    -- Command Port
   cmd_valid_in         => cmd_valid_in,  -- Command Valid, 1 cycle

   -- Data port
   data                 => data      ,    -- Data out Port
   data_valid           => data_valid,    -- Data Valid, 5 cycles

   -- Error Signals
   cmd_error           => cmd_error  -- Invalid command
);

entity test_entity is
port(
      -- some command without colons
      clk : in std_logic;
      -- one word: some description
      force_block_done_active_i   : in std_logic;
      -- direct access: set block_done signal to inactive
      force_block_done_inactive_i : in std_logic;
      -- direct access: directly output this manual values to DACs
      force_block_done_inactive_i : in std_logic
);
end entity;

component test_entity
port (
	clk    : in  std_logic;
	word   : some description        force_block_done_active_i   : in std_logic;
	access : set block_done signal to inactive        force_block_done_inactive_i : in std_logic;
	access : directly output this manual values to DACs        force_block_done_inactive_i : in std_logic
);
end component test_entity;

test_entity_i : test_entity
port map (
	clk    => clk,
	word   => word,
	access => access,
	access => access
);

signal clk    : std_logic;
signal word   : description        force_block_done_active_i   : in std_logic;
signal access : block_done signal to inactive        force_block_done_inactive_i : in std_logic;
signal access : output this manual values to DACs        force_block_done_inactive_i : in std_logic;

entity test is
    generic(
        constant something: integer := 40;
        constant another_thing: time := 1 ns
    );
    port(
        c: out std_logic
    );
end entity;

component test
generic (
    something     : integer := 40;
    another_thing : time := 1
);
port (
    c : out std_logic
);
end component test;

diff --git a/lib/templates.js b/lib/templates.js
index ad9c748..d146854 100644
--- a/lib/templates.js
+++ b/lib/templates.js
@@ -68,7 +68,7 @@ function instanceTemplate(entity) {
     longest = longestinArray(entity.ports, "name")
     for (port of entity.ports) {
       name = port.name.rpad(" ", longest)
-      text += `  ${name} => ${port.name},\n`
+      text += `  ${name} => s_${port.name},\n`
     }
     // Strip the final comma
     text = text.slice(0, -2)
@@ -85,7 +85,7 @@ function signalsTemplate(entity) {
     longest = longestinArray(entity.ports, "name")
     for (port of entity.ports) {
       name = port.name.rpad(" ", longest)
-      text += `signal ${name} : ${port.type};\n`
+      text += `signal s_${name} : ${port.type};\n`
     }
   }
   return text