- ๐ Hi, Iโm Sina Soltani @sinasoltani123
- ๐ Iโm interested in AI, music , neuroscience, genetics and the universe
- ๐ฑ Iโm currently learning RL,DNNs
- ๐๏ธ Iโm looking to collaborate on anything AI related
- ๐ซ How to reach me [email protected]
sinasoltani123 / 32-bit-pipelined-mips-processor-implemented-using-verilog-with-booth-multiplication-algorithm Goto Github PK
View Code? Open in Web Editor NEW32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite