shuyunjia / baremetal-plic Goto Github PK

Hi Team ,
I am using the baremetal- plic code , We are facing an issue could you please help us to resolve it

I am using mmio port , I am doing some AXI transaction , In between transaction we are generating Interruptus,
mcause value is changed form 0x80000003 to 0x8000000b saying that Interrupt is triggered ,during this time I am not seeing any AXI transaction this is expected Once I get plic_complete Processor should start the AXI transaction again but it is not happen ,
mcause value goes to 1 saying instruction access failed .

below is the snippet

int main(int argc, char** argv);
int main(int argc, char** argv)
{

//init plic
PLIC_init(&plic0, 0x0c000000, 2, 1);
plic_source int_spi0 = 11;
PLIC_enable_interrupt(&plic0, int_spi0);
PLIC_set_priority(&plic0, int_spi0, 1);

set_csr(mie,MIP_MEIP);
while (adr_s < 0x20003010 ) {
Write64 (adr_s,adr_s);
adr_s = adr_s + 0x1;
}
adr_s=0x20000000;
while (adr_s < 0x20003010 ) {
d_read= reg_read64(adr_s);
d_write = adr_s;
adr_s=adr_s+0x1;
if (d_read != d_write) {
//write_fail(adr_s,d_read);
while(1);
}
}
while(1);
return 0;