- ๐ Graduate engineer at Arm Austin
- ๐ซ EFZ '17 | SJTU '21 | CMU '23
- ๐ญ Interested in computer architecture (don't like reading papers)
- ๐ฑ Currently learning digital IC design & verification & skiing (especially skiing)
- ๐ฅฅ Good at making coconut desserts (zzzzz)
- ๐ Eat watermelons every summer... (and winter)
- ๐ค Sleep 12 hours every day... (people who don't like me sleep double time every day)
- ๐ซ How to reach me: [email protected]
shili2017 / rocket-chip-inclusive-cache Goto Github PK
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An RTL generator for a last-level shared inclusive TileLink cache controller
License: Apache License 2.0