shangdawei / rfid-reader Goto Github PK

The circuit used for carier frequency generation is simply overkill and 
uses too much hardware for what it does. 

The circuitry was adopted from the microchip reference design. In their 
design a single crystal was used to generate both the clock for the 
microchip and, with the aid of a divider, the carier signal to be fed into 
the antenna driver.

In our design the chip is using an internal oscillator, so there is no 
need for an external clock. Hence the only function being served by the 
clock circuitry is to generate a carrier for the antenna. However it is 
still using a 4 MHz crystal and the divider to get the 125 kHz carier 
signal that we need. Also, the signal being generated is a square wave and 
has to be passed through a series RLC circuit in the next stage to 
transform it into a sinusoid.

The task is to replace the clock generating circuitry and the RLC 
combination with something that generates a 125 kHz sinusoidal to be fed 
directly into the driving stage. Feel free to attack the issue.

We can improve the filtering stage (read minimize the hardware) by 
replacing the two active band pass filters with a single bandpass filter 
utilizing a single opamp.

The task is to see if this is a feasible improvement over what we have 
now. Myself and Valentine were able to get a frequency response of the 
current filters using Cadence PSpice. The next step is to find a single 
opamp filter configuration and drop it in place of the current set up to 
get the new response. From there we can see if it is a proper substitute.