Generator of SystemC, VHDL and SystemVerilog projects.

River CPU and peripheries libraries have different RTL implementation versions: System Verilog and VHDL (see riscv_vhdl project). It is quite compilcate to maintain the precise SystemC that matches to these RTL implementations. To support consistency of all these implementations (SystemC, SystemVerilog and VHLD) this generator is used.

• Preserve project structure and files
• Support commentaries in the same way as in the current manual implementation
• Dynamically track global and local configuration parameters to compute their values
• Preserve text names of configuration parameters in the signal bus declarations
• Automatically detect unconnected IO-ports
• Avoid and fixing latches instead of FFs.

• librtlgen library that implements API with the generic C++ classes which are used to describe any RTL model: project, file, parameter, module, port, signal etc.
• rivergen RTL project implements River CPU using librtlgen generic classes.

// Code comment
localparam int CFG_PARAM1 = 128;
localparam int CFG_PARAM2 = CFG_PARAM1 - 64;    // comment 2

logic [CFG_PARAM1-1:0] A;
logic [CFG_PARAM1-CFG_PARAM2-1:0] B;

// Code comment
static const int CFG_PARAM1 = 128;
static const int CFG_PARAM2 = CFG_PARAM1 - 64;  // comment 2

sc_biguint<CFG_PARAM1> A;
sc_uint<CFG_PARAM1-CFG_PARAM2> B;

Generator preserves all parameter names and automatically calculates bus widths to properly use sc_uint/sc_biguint definitions.

Windows: Use CMake and generate MS Visual Studio project.

Linux:

> cd rtlgen
> cmake -S . -B output_dir
> cd output_dir
> make
> ./bin/rivergen

• System Verilog
• SystemC