A VS Code extension bundling all the things I want in a System Verilog IDE.

The project draws from multiple projects:

• https://github.com/chipsalliance/verible
• https://github.com/eirikpre/VSCode-SystemVerilog
• https://github.com/mshr-h/vscode-verilog-hdl-support
• https://github.com/TerosTechnology/vscode-terosHDL
• https://github.com/bkromhout/vscode-tcl/tree/master

The language server provides a couple of features from the Verible SystemVerilog productivity suite right in the editor.

• Linting: Checks your code against a number of lint rules and provides 'wiggly lines' with diagnostic output and even offers auto-fixes when available.
• Configuration: Linting configuration is now sourced from an SVN repo so that teams can work from the same set of rules. @see Prerequisites below.
• Formatting: Offers Format Document/Selection according to the Verible formatting style. The 'look' can be configured if needed.
• Outline: Shows the high-level structure of your modules and functions in the outline tree. Labelled begin/end blocks are also included.
• Hover: Highlight symbols related to the one under the cursor.
• Go-To-Definition: Jump to the definition of the symbol under the cursor.
• Go-To-References: Jump to the references of the symbol under the cursor.
• AUTO-expansion: Features known from Emacs Verilog-mode, used for expanding various /*AUTO...*/ pragmas in Verilog and SystemVerilog code. These expansions are available as code actions.
  • AUTOARG – generates a list of non-ANSI ports in a module header,
  • [🎉 New] AUTOINST with AUTO_TEMPLATE – generates connections in a module instance based on the instantiated module's ports,
  • [🎉 New] AUTOINPUT, AUTOOUTPUT, AUTOINOUT – declares ports based on connections generated by AUTOINST,
  • [🎉 New] AUTOWIRE – declares wires based on connections generated by AUTOINST,
  • [🎉 New] AUTOREG – declares regs for outputs not connected to any module instance.

1. An SVN repo with a copy of the verible-verilog-ls.exe and .rules.verible_lint file. A copy of verible and associated rules file are included with this extension, but users will need to add these to their SVN repo.
2. In the exteions settings, set the svn_path in stevesSystemVerilogExtension.rules_config.svn_path to point to the SVN repo.