I am a senior undergraduate student and an undergraduate researcher at the department of Electronics and Communication Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG). I am passionate about Programming, Digital VLSI design and hardware prototyping on FPGAs.
saursin / rvsim_old Goto Github PK
View Code? Open in Web Editor NEWA RISC-V ISA simulator in C++
License: MIT License