sandilsranasinghe / digital-lab-9 Goto Github PK

Component to make - Register Bank
Relevant file - Reg_Bank.vhd

• Create a branch for developing this (reg_bank)
• Create register component to use for individual registers
• Import decoder units from previous labs if necessary
• Check if needed to optimize any imports
• Implement component logic
• Create testbench
• Verify Simulation

Note:

• Currently thinking of using a single 32-bit bus as output, we can use the relevant indices for connecting each register output here. Not much of a logical difference, but will reduce code.

Component to make - 3-bit Adder
Relevant File - Adder_3.vhd

• Create a branch for developing this (3_bit_adder)
• Implement component logic
• Make Testbench
• Verify Simulation

Notes:

• Sub components used for #3 can probably be used here (half adder, full adder)
• As mentioned in #6 , since this is fairly small it is better if it is done with the program counter
• Note that one of the bus inputs will have to be hardwired to one here. Need to decide if that will be done in the component itself or only when using the component. Probably better to do it when using.

Component to make - Program Counter
Relevant files - Program_Counter.vhd

• Create a branch for developing this (program_counter)
• Implement component logic
• Make Testbench
• Verify Simulation

Notes:

• This will probably be very similar to the register component used for #2 . See if it can be used here
• Since this is relatively small it will be good if this can be done with the 3-bit adder which is connected to this, since that too will be having a lot in common with the 4-bit add/sub unit.
• Might need an enabling input from the Instruction Decoder as mentioned in #5

Component to make - 4-bit Add/Sub unit
Relevant file - Add_Sub_4.vhd

• Create a branch for developing this (add_sub_unit)
• Import any necessary sub components (half adder, full adder maybe)
• Check if any imports can be optimized
• Implement addition logic
• Discuss how subtract works
• Implement subtract logic
• Create testbench
• Verify simulation

Notes:

• Add any other IO if absolutely needed, but try to minimize things that we can do without

Component to make - Program ROM
Relevant file - Program_ROM.vhd

• Create a branch for developing this (program_rom)
• Implement component logic
• Decide if we need a testbench

Notes:

• A rom was used in a previous lab, the code will probably be similar

Component to make - Instruction Decoder
Relevant file - Instruction_Decoder

• Create a branch for developing this (instruction_decoder)
• Figure out how instructions with multiple cycles will work
• Implement logic for recognizing instructions
• Implement logic for MOVI
• Implement logic for ADD
• Implement logic for NEG
• Implement logic for JZR
• Create Testbench
• Verify Simulation

Notes:

• Might need to give an enabler input to the Program Counter
• Need to figure out the instruction cycles and the point at which the PC is incremented

There are several different multiplexers in the design. We should be able to have a significant amount of common code in between them.

Components to make - 2way-3bit MUX, 2way-4bit MUX, 8way-4bit MUX
Relevant files - Mux_2_3.vhd, Mux_2_4.vhd, Mux_8_4.vhd

• Create a branch for developing these (mux)
• See what can be reused from our decoder/mux implementations from previous labs
• Check if any imports can be optimized
• Create any common sub components needed
• Implement component logic
• Create testbench
• Verify Simulation

Notes:

• I doubt us being able to use Mux_8_to_1 which we had built in previous labs directly.
• We will need to test each different mux separately just to be safe