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This is a repository for the copy of submitted and accepted project files in the "Computer Organization" course in School of Computer Science and Engineering(SCSE),Beihang University. All the projects files in this repository are finished during the autumn semester of 2018-2019(1st semester of Grade 2)
This repository contains the following projects:

*Project3: Monocycle CPU implemented and simulated by Logisim

*Project4: Monocycle CPU implemented and simulated by Verilog (Xinlix ISE and ISIM)

*Project5: 5-stage Pipeline CPU implemented and simulated by Verilog (Xinlix ISE and ISIM)
-achieved hazard control (stall/forward) and branch delayed slot
-support a mips instruction set containing 11 instructions

*Project6 (for HAC Honor College(23rd faculty)): 5-stage Pipeline CPU (supporting Interrupt Request and Exception )
-implemented and simulated by Verilog (Xinlix ISE and ISIM)
-supporting Interrupt Request and Exception

*Project6 (for SCSE (6th faculty)): 5-stage Pipeline CPU implemented and simulated by Verilog (Xinlix ISE and ISIM)
-support a mips instruction set containing 50 instructions
-support integer multiplication and division

*Project7: 5-stage Pipeline CPU （the combination of P6 HAC version and Non-HAC version）
supporting Interrupt Request and Exception
-support a mips instruction set containing 50 instructions
-support integer multiplication and division

*Project 8: 5-stage Pipeline CPU (FPGA,hardware and software interface)
-support I/O
--support uart transmission( implementing this function with interrupt request)
--support 8-digit digital tube
--support user keyboard
-contains 3 mips code which implement a calculator, a uart-transmission test,a counter on the 5-stage CPU
-bit files are generated ,loaded and tested on Xilinx Spartan6 XC6SLX100 FPGA board,speed leve 2,package FGG676