rpg-7 Goto Github PK

noneuclidean

A Non-Euclidean Rendering Engine for 3D scenes.

oc8051

download from opencores.org

oc_mkjpeg

Fork of the mkjpeg project from OpenCores

ocm-pld-dev

Anlogic chip support for MSX project

oh

Silicon proven Verilog library for IC and FPGA designers

omniscent

Analyze of Mekka & Symposium 1997 PC 4K 1st "Omniscent"

openeda

Open source EDA chip design flow

openfpga

OpenFPGA

openram

An open-source static random access memory (SRAM) compiler.

openx86

opl3_fpga

Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

paskisoc

PaserTech PaskiSoC 一个低成本的riscv soc实现, 支持32bit linux with mmu

pcr16

PCR16孔核酸检测仪

polyphony

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

prv32_soc

Pan's PRV32 Core, SoC Suite by Hong Xiaoyu

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

pyverilog_toolbox

r8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

reactos

GitHub clone of SVN repo svn://svn.reactos.org/reactos/trunk/reactos/ (cloned by http://svn2github.com/). This repo is not updated anymore. Please read at http://piotr.gabryjeluk.pl/blog:svn2github-problems

redpanda-cpp

A light-weight C/C++ IDE based on Qt

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

risc-v_soc_panxy

For FPGAChina Competition

riscv-cocotb

cocotb infrastructure for RISC-V core testing

rotorcpu

Embedded multi-core processor

rtl-automata

RTL-AUTOMATA is a RTL automatic build script based on shell script and makefile.

ruce

Rocaloid UTAU Compatible Engine

rv51

A RISC-V emulator for the 8051 (MCS-51) microcontroller.

sandnix

A Unix-like POSIX-compatible operating system.

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

serv

SERV - The SErial RISC-V CPU