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BUAA CO

P0:Logisim

课下测试:搭建 CRC 校验码计算电路,ALU,正则表达式匹配

课上测试:Logisim 完成部件及 FSM 设计

P1:Verilog-HDL

课下测试:实现 splitter, ALU,格雷码计数器,合法表达式识别,走迷宫

课上测试:Verilog-HDL 完成部件及 FSM 设计

P2:MIPS

课下测试:矩阵乘法、排序、回文串判断

课上测试:选择题+编程题

P3:Logisim 单周期 CPU

课下测试:完成支持 7 条指令的单周期 CPU 设计

课上测试:新增指令

P4:Verilog 单周期 CPU

课下测试:完成支持 7 条指令的单周期 CPU 设计

课上测试:新增指令

P5:Verilog 流水线 CPU(1)

课下测试:完成支持 10 指令流水线 CPU 设计

课上测试:流水线工程化方法

P6:Verilog 流水线 CPU(2)

课下测试:完成支持 50 指令流水线 CPU 设计

课上测试:流水线工程化方法

P7:异常中断支持

课下测试:完成微型 MIPS 系统设计,开发简单 I/O,验证中断

课上测试:现场测试

P8:FPGA

2020 级取消 P8(悲)

后记

具体教程可参考我的博客:计算机组成实验

这里有我写的一个 Verilog 反编译器:DASM

其中我先做了 P6 再做 P5,避免了做 P6 时大规模的重构。

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