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RgGen

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RgGen

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.

RgGen has following features:

  • Generate source files related to CSR from register map specifications
    • RTL module
      • SystemVerilog
      • Verilog
      • VHDL
      • Supports standard bus protocols
        • AMBA APB
        • AMBA AXI4-Lite
        • Wishbone
    • UVM register model (UVM RAL/uvm_reg)
    • C header file
    • Register map documents written in Markdown
  • Register map specifications can be written in human readable format
    • Ruby with APIs to describe register map information
    • YAML
    • JSON
    • TOML
    • Spreadsheet (XLSX, ODS, CSV)
    • SiFive DUH
  • Plugin feature
    • Allow you to customize RgGen for your environment
      • Add your own special bit field types
      • Add your own host bus protocol

Installation

Ruby

RgGen is written in the Ruby programing language and its required version is 3.0 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see this page.

Installatin Command

RgGen depends on following sub components and other Ruby libraries.

To install RgGen and the dependencies, use the command below:

$ gem install rggen

RgGen and dependencies will be installed on your system root.

If you want to install them on other location, you need to specify install path and set GEM_PATH and PATH environment variables:

$ gem install --install-dir /path/to/your/install/directory rggen
$ export GEM_PATH=/path/to/your/install/directory
$ export PATH=$GEM_PATH/bin:$PATH

You would get the following error message duaring installation if you have the old RgGen (version < 0.9).

ERROR:  Error installing rggen:
        "rggen" from rggen-core conflicts with installed executable from rggen

To resolve the above error, there are three solutions. See this page

Docker Image

The rggen-docker is a Docker image to simplify installation and use of RgGen. You can also execute RgGen by using this image:

$ docker run -ti --rm -v ${PWD}:/work --user $(id -u):$(id -g) rggendev/rggen-docker:latest -c config.yml -o out block_0.yml

See the rggen-docker repository for further details.

Usage

See Wiki documents.

Plugin

RgGen has plugin feature to allow your cusomization. See this Wiki document for futher detals.

Supported Tools

Following EDA tools can accept the generated source files.

  • Simulation tools
    • Synopsys VCS
    • Cadence Xcelium
    • Metrics DSim
    • Xilinx Vivado Simulator
    • Verilator
      • Need -Wno-unoptflat switch for Verilog RTL
    • Icarus Verilog
      • Verilog RTL only
  • Synthesis tools
    • Synopsys Design Compiler
    • Intel Quartus
    • Xilinx Vivado
    • Yosys
      • Verilog RTL

Example

You can get sample configuration file and register map specification from the rggen-sample repository. This register map specification is for a UART IP.

You can try to use RgGen by uisng these example files. Hit command below:

$ rggen -c config.yml -o out uart_csr.yml
  • -c: Specify path to your configuration file
  • -o: Specify path to the directory where generated files will be written to

Then, generated files will be written to the out directory.

If you want to generate Verilog RTL and/or VHDL RTL then you need to instll optional plugins listed below.

$ gem install rggen-verilog
$ gem install rggen-vhdl

In addition, you need to tell RgGen to use these plugins by using the --plugin option switch:

rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl uart_csr.yml

RgGen will generate following source files from the uart_csr.yml register map specification:

Contributing

See Contributing Guide.

Contact

Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:

See Also

Copyright & License

Copyright © 2019-2024 Taichi Ishitani. RgGen is licensed under the MIT License, see LICENSE for futher detils.

Code of Conduct

Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the code of conduct.

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rggen-sv-rtl's Issues

Quartus support

Info: *******************************************************************
Info: Running Quartus Prime Analysis & Elaboration
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 6 01:30:53 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off block_0 -c block_0 --analysis_and_elaboration
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_rtl_pkg.sv
Info (12022): Found design unit 1: rggen_rtl_pkg (SystemVerilog)
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_register_if.sv
Info (12023): Found entity 1: rggen_register_if
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_register_common.sv
Info (12023): Found entity 1: rggen_register_common
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_mux.sv
Info (12023): Found entity 1: rggen_mux
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_indirect_register.sv
Info (12023): Found entity 1: rggen_indirect_register
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_external_register.sv
Info (12023): Found entity 1: rggen_external_register
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_default_register.sv
Info (12023): Found entity 1: rggen_default_register
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bus_if.sv
Info (12023): Found entity 1: rggen_bus_if
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01trg.sv
Info (12023): Found entity 1: rggen_bit_field_w01trg
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01src.sv
Info (12023): Found entity 1: rggen_bit_field_w01src
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01s.sv
Info (12023): Found entity 1: rggen_bit_field_w01s
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01crs.sv
Info (12023): Found entity 1: rggen_bit_field_w01crs
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_w01c.sv
Info (12023): Found entity 1: rggen_bit_field_w01c
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rws.sv
Info (12023): Found entity 1: rggen_bit_field_rws
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwl.sv
Info (12023): Found entity 1: rggen_bit_field_rwl
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwe.sv
Info (12023): Found entity 1: rggen_bit_field_rwe
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rwc.sv
Info (12023): Found entity 1: rggen_bit_field_rwc
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rw_wo.sv
Info (12023): Found entity 1: rggen_bit_field_rw_wo
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rs.sv
Info (12023): Found entity 1: rggen_bit_field_rs
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_ro.sv
Info (12023): Found entity 1: rggen_bit_field_ro
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_reserved.sv
Info (12023): Found entity 1: rggen_bit_field_reserved
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_rc.sv
Info (12023): Found entity 1: rggen_bit_field_rc
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_bit_field_if.sv
Info (12023): Found entity 1: rggen_bit_field_if
Info (12021): Found 0 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_backdoor_pkg.sv
Info (12021): Found 0 design units, including 0 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_backdoor_if.sv
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_if.sv
Info (12023): Found entity 1: rggen_axi4lite_if
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_bridge.sv
Info (12023): Found entity 1: rggen_axi4lite_bridge
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_axi4lite_adapter.sv
Info (12023): Found entity 1: rggen_axi4lite_adapter
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_if.sv
Info (12023): Found entity 1: rggen_apb_if
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_bridge.sv
Info (12023): Found entity 1: rggen_apb_bridge
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_apb_adapter.sv
Info (12023): Found entity 1: rggen_apb_adapter
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_address_decoder.sv
Info (12023): Found entity 1: rggen_address_decoder
Info (12021): Found 1 design units, including 1 entities, in source file /home/cra2ypierr0t/rggen-sv-rtl/rggen_adapter_common.sv
Info (12023): Found entity 1: rggen_adapter_common
Info (12021): Found 1 design units, including 1 entities, in source file out/block_0.sv
Info (12023): Found entity 1: block_0
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(111): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(127): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(143): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(159): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(94): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(193): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(176): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(227): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(237): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(247): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(258): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(210): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(283): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(299): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(315): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(328): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(266): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(359): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(376): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(393): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(403): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(342): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(436): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(451): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(466): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(482): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(498): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(513): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(528): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(543): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(558): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(573): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(419): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(606): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(624): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(642): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(652): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(670): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(688): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(698): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(714): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(589): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(748): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(763): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(778): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(793): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(731): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(828): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(847): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(865): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(809): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(911): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(930): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(886): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(973): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(952): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(1011): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(990): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at block_0.sv(1028): conditional expression evaluates to a constant
Info (12127): Elaborating entity "block_0" for the top level hierarchy
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_0" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_1" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_2" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_9_bit_field_0" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_9_bit_field_1" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_0" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_1" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_8_bit_field_2" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_9_bit_field_0" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "o_register_9_bit_field_1" into its bus
Info (12128): Elaborating entity "rggen_register_if" for hierarchy "rggen_register_if:register_if[22]"
Info (12128): Elaborating entity "rggen_apb_adapter" for hierarchy "rggen_apb_adapter:u_adapter"
Warning (10230): Verilog HDL assignment warning at rggen_apb_adapter.sv(19): truncated value with size 16 to match size of target (8)
Info (12128): Elaborating entity "rggen_bus_if" for hierarchy "rggen_apb_adapter:u_adapter|rggen_bus_if:bus_if"
Info (12128): Elaborating entity "rggen_adapter_common" for hierarchy "rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common"
Warning (10036): Verilog HDL or VHDL warning at rggen_adapter_common.sv(46): object "status" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at rggen_adapter_common.sv(47): object "read_data" assigned a value but never read
Warning (10241): Verilog HDL Function Declaration warning at rggen_mux.sv(7): function "mux" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function
Warning (10030): Net "u_status_mux.mux" at rggen_mux.sv(7) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "u_read_data_mux.mux" at rggen_mux.sv(7) has no driver or initial value, using a default initial value '0'
Info (12128): Elaborating entity "rggen_mux" for hierarchy "rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common|rggen_mux:u_status_mux"
Info (12128): Elaborating entity "rggen_mux" for hierarchy "rggen_apb_adapter:u_adapter|rggen_adapter_common:u_adapter_common|rggen_mux:u_read_data_mux"
Info (12128): Elaborating entity "rggen_bit_field_if" for hierarchy "rggen_bit_field_if:g_register_0.bit_field_if"
Info (12128): Elaborating entity "rggen_default_register" for hierarchy "rggen_default_register:g_register_0.u_register"
Info (12128): Elaborating entity "rggen_register_common" for hierarchy "rggen_default_register:g_register_0.u_register|rggen_register_common:u_register_common"
Warning (10230): Verilog HDL assignment warning at rggen_register_common.sv(36): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at rggen_register_common.sv(38): truncated value with size 32 to match size of target (8)
Error (10207): Verilog HDL error at rggen_register_common.sv(117): can't resolve reference to object "mux"
Error (10903): Verilog HDL error at rggen_register_common.sv(97): failed to elaborate task or function "get_read_data"
Error (12152): Can't elaborate user hierarchy "rggen_default_register:g_register_0.u_register|rggen_register_common:u_register_common"
Error: Quartus Prime Analysis & Elaboration was unsuccessful. 3 errors, 68 warnings
Error: Peak virtual memory: 1256 megabytes
Error: Processing ended: Thu Feb 6 01:31:04 2020
Error: Elapsed time: 00:00:11
Error: Total CPU time (on all processors): 00:00:27

Hierarchical lookup error on Xcelium simulator

Xcelium cannot find the 'at_clock_edge identifier. Need workaround.

    if (!backdoor_cb.at_clock_edge.triggered) begin
                                           |
xmelab: *E,CUVUNF (/home/kazt81/work/rggen-sample-testbench/rtl/rggen-sv-rtl/rggen_backdoor_if.sv,66|43): Hierarchical name component lookup failed for 'at_clock_edge' at 'top.u_block_0.g_register_9.g[0].u_register.u_register_common.u_backdoor.backdoor_if'.

refs: taichi-ishitani/tvip-axi#31 (comment)

Support posted write access

Support posted write access.

  • Introduce access field to rggen_bus_if and rggen_register_if
    • 0b01: Posted write
      • Able to assert ready immediately when request is accepted
    • 0b11: Non-posted write
      • Assert ready when response arrives
    • 0b10: Read
  • Remove write field from rggen_bus_if and rggen_register_if

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