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vhdl-mode's Introduction

VHDL Mode

Overview

This package attempts to recreate the functionality found in the well-loved language mode in Emacs. The extensibility of Sublime Text makes it an excellent platform upon which to attempt this.

This package may stand alone, however it was created to co-exist peacefully along with the Emacs Pro Essential package. In that same vein, the keyboard shortcuts were designed around the vhdl-mode shortcuts in Emacs. Additionally, there is now a Preferences setting that activates the Emacs vhdl-mode keybinds if desired.

Initially, the package relied upon the TextMate syntax file by Brian Padalino (after conversion to the ST3 YAML format). However after working with this syntax definition, it became apparent that this syntax definition did not conform well to current scoping best practices (noticable with color schemes) and had some issues with certain syntactical structures. An effort was undertaken to rewrite the syntax file from the language reference and incorporate meaningful and fine grained lexical scopes.

If any bugs are found or feature requests are desired, please visit either:

I will state up front that I cannot duplicate Emacs vhdl-mode perfectly (e.g. see the discussion on stutter typing). However if there is a particular omission or a feature that is desireable, please feel free to open an issue. I'm happy to investigate and attempt implementation.

Feature Set

  • Syntax file supporting highly granular scoping of lexical structures. VHDL-2008 is supported pretty well. VHDL-2019 is not yet supported.
  • Port copying from entity or component declarations.
    • May be pasted as entity, component, signals, direct entity instantiations, or testbench.
    • Ports may be flattened or reversed.
    • Instantiation insertion is 'smart' in that it will not duplicate an already existing instantiation name.
    • Accessible via keybind or right click context menu.
  • Subprogram coping from a declaration or specification.
    • May be pasted as a declaration, body, or call.
    • Parameters may be flattened.
    • Accessible via keybind or right click context menu.
  • Stutter typing shortcuts for the assignment operators and commenting structures.
  • Templates in the form of snippets for commonly used structures.
    • Header template is further customizable through settings and will update a time field on save.
  • Code beautification supporting several parenthetical code styles natively (Kernigan & Ritchie, Allman, and Lisp)
  • Sublime Text Goto symbol and definition support, both local and global for source tree navigation.
  • Region comment/uncommenting. Also handles the continuous commenting behavior of Emacs vhdl-mode. While writing a comment line, if the final character before hitting Enter is a space, the next line will also be a comment, with the commenting characters automatically inserted.

Related Packages

  • Emacs Pro Essentials by sublime-emacs : The VHDL Mode package will work without this package, however if you are coming from Emacs vhdl-mode, you may find this package useful. Also see the setting for turning on Emacs vhdl-mode keybinds.
  • HDLProject by bootsiaz : It's the closest thing to Emacs vhdl-mode Speedbar that I know of. This clever implementation leverages symbolic links to make use of Sublime Text's Sidebar for hierarchical project display.

Dependencies

  • ruamel.yaml : This will be installed by Package Control automatically as part of installing the package if it is not already present.

Future Design Goals

  • Improved scoping and any feature that seems reasonable.

Usage

Configuration

The VHDL Mode sublime-settings file contains fields that are used to fill in certain fields in the header template upon insertion. A user override may be created by selecting Preferences >> Package Settings >> VHDL Mode >> Settings. This will bring up the default settings file and a User variation on the settings. To customize the fields, simply copy and paste the defaults over to the User override file, and edit to taste.

These fields can also be set in the sublime-project file under "settings" for project specific behavior. To facilitate this, a project helper snippet was created to inject these settings when editing the project file. Simply select Project >> Edit Project from the menu, move the cursor past the "folders" line and type project and hit Tab for the snippet completion. The project snippet also creates a couple of sample build methods that can be used for the project.

One particular setting meshes with both the header template and the on-save time field. The vhdl-modified-time-string setting is the string that the code looks for when catching the on-save event, and updating that field. This should only be altered if the header snippet has been modified. When the event triggers, the code searches for that string, and replaces that line with the string, plus the time information.

Code beautification should pay attention to the tab_size and translate_tabs_to_spaces settings that are part of the standard Sublime Text preferences. Please let me know if this causes any issues.

  • vhdl-user : String : Fills in the username portion of the header template.
  • vhdl-company : String : Fills in the company name portion of the header template.
  • vhdl-project-name : String : Fills in the project name portion of the header template. This one is a good candidate for customizing in the sublime-project file!
  • vhdl-platform : String : Fills in the platform or part number portion of the header template.
  • vhdl-standard : String : Fills in the coding standard portion of the header template.
  • vhdl-line-length : Integer : This value is used for determining the length of line for comment "lines" generated. Defaults to 80 characters.
  • vhdl-modified-time-string : String : Represents the string that will be searched for when the file is saved. If this is found, that line is replaced with a string comprising of this pattern, plus the current time. This is also used in the header creation to make sure that header template insertion injects the correct string.
  • vhdl-use-copyright-block : Boolean : Setting this to true will make the header template insertion inject the copyright block. Setting this to false will make it such that this section is not used.
  • vhdl-copyright-block : String List : This list of strings will be joined by newlines and prepended by a newline (required due to the optional nature of this block -- see the snippet field location) and is used when vhdl-use-copyright-block is set to true. This string will be searched for ${YEAR} and ${COMPANY} and replaced by the current year, and the vhdl-company string respectively. The string list is required since JSON does not allow multiline strings. This block now also supports ${LINE} to generate a line matching the vhdl-line-length parameter.
  • vhdl-use-revision-block : Boolean : Setting this to true will make the header template insertion inject the revision block. Setting this to false will make it such that this section is not used.
  • vhdl-revision-block : String List : This list of strings will be joined by newlines and prepended by a newline. It is used when vhdl-use-revision-block is set to true. This block now also supports ${LINE} to generate a line matching the vhdl-line-length parameter.
  • vhdl-emacs-keybinds : Boolean : This setting must be set in the User's Preferences, and not the VHDL Mode package settings. When set true this activates a second set of keybindings that are identical to the Emacs vhdl-mode keybindings. WARNING!!! This should NOT be used unless the user is using Emacs Pro Essentials and is familiar with Emacs keybindings. The trigger key for most Emacs code functions starts with C-c which is really going to mess with your head if you're expecting that to be the typical Windows Copy command.

Key Mappings

As mentioned, the goal here was to be familiar with Emacs vhdl-mode users. However I am well aware that I'm also in a Windows environment, and the commonly used C-c prefix for code mode commands in Emacs will conflict with the standard Windows copy command. Sublime Text 3 frequently uses M-k as an extension keymap and this seemed a suitable replacement (in the Windows environment the Meta key is Alt). The key mappings are also context selected, so should not trigger on anything that is not a source.vhdl file.

Another note, these are sequence keystrokes. For example to copy a port interface from an entity, move the point into the structure (anywhere should be fine) and hit Alt-k then p then w. These should not be chorded.

For the long-time Emacs vhdl-mode user, there is now a preference for activating the original Emacs vhdl-mode keybinds. I am not going to document these here as it will likely confuse new users however if interested, simply look at the Default (Windows|OSX|Linux).sublime-keymap file for the keybinds.

Port Interface Copy/Paste Functions

It may help to remember p for port, then w for write (to buffer). The other mnemonics are fairly straightforward. These commands are also available with the right-click context menu under the VHDL Mode heading.

  • Copy Ports : M-k p w
  • Paste as Signals : M-k p s
  • Paste as Component: M-k p c
  • Paste as Entity: M-k p e
  • Paste as (Direct Entity) Instance: M-k p i
  • Paste as Testbench: M-k p t -- Opens a new view and fills out boilerplate material with the interface as the unit under test.
  • Flatten ports: M-k p f -- An interface clause with multiple names on one line is flattened into one name per line.
  • Reverse ports: M-k p r -- The direction of ports is reversed: in become out, and out or buffer becomes in.

The following animated GIF demonstrates a portion of the port copying feature.

Port Copying Demonstration

Subprogram Interface Copy/Paste Functions

It may help to remember s for subprogram, then w for write (to buffer). Much like the port version of this feature, the mnemonics are straightforward. These commands are also available with the right-click context menu under the VHDL Mode heading.

  • Copy Subprogram : M-k s w
  • Paste as Declaration : M-k s d
  • Paste as Body : M-k s b
  • Paste as Call : M-k s c
  • Flatten parameters: M-k s f -- An interface clause with multiple names on one line is flattened into one name per line.

Commenting

It may help to remember 'c' for code, then 'c' for comment, 'b' for beautify, etc. These commands are also available with the right-click context menu under the VHDL Mode heading.

  • Toggle Comment Region : M-k c c
  • Beautify Entire Buffer : M-k c b

Template

Largely templating is handled by the snippet system, however the header is a special feature as it inserts various fields automatically. Remember 't' for template and 'h' for header. These commands are also available with the right-click context menu under the VHDL Mode heading.

  • Insert Header : M-k t h

Miscellaneous

  • Package Version : M-k v
  • Scope at Point : M-k S
  • Build : C-c C-k -- Only if vhdl-emacs-keybinds is set to true. Otherwise the Sublime Text 3 default keybind of F7 will run build.
  • Auto matching double quotes : Additional source specific variation on this keybind to permit leading characters (oOxX) for VHDL octal and hexadecimal literals.

Stutter Typing

In Emacs vhdl-mode, double striking some keys will insert some syntactical punctuation elements. Unfortunately, I cannot duplicate the entire Emacs vhdl-mode stutter typing repetoire since I do not have access to the keystream directly. What I have been able to do is use keybindings and in one case a keybinding plus a macro to replicate the behavior. I'll list the implemented replacements and then a note on the ones I cannot and why I cannot replicate these. The symbols below will have a space on either side of them which is difficult to see in this HTML documentation.

  • ;; : Produces :
  • ;;; : Produces := (See notes below)
  • .. : Produces =>
  • ,, : Produces <=
  • --- : Produces a comment line extending to the column set by the vhdl-line-length setting (default: 80) starting where the cursor is, and accounting for tabs. This one pays attention to the tab_size Preference if you use tabs. If the cursor is beyond the defined line length, the line will simply be a two character comment -- and produce a warning in the console.
  • --= : Produces a three-sided comment box extending to the column set by the vhdl-line-length setting (default: 80) starting where the cursor is, and accounting for tabs. If the cursor is beyond the defined line length, the box will simply be bounded by -- above and below (not a "line"), and a warning will be produced in the console. (See notes on variation from the original Emacs vhdl-mode ---- box.)

The following are the stutter typing replacements I cannot do.

  • [, [[, ], ]] : These cannot be duplicated properly. The problem is that the Sublime API does not have direct access to the keystream. The only way to replicate this (as I was able to with ;;;) is to create a keybind that checks the preceding text and if it is the replaced text, execute a macro that deletes and replaces the text with the new text. However if I replaced [ with ( and then looked for a preceding paren for [[ then one would never be able to properly type nested parenthesis.
  • '' : This interferes with the auto-completion feature in Sublime Text so I have opted to not implement it.
  • ;;; : I'd like to give fair warning that this is not implemented exactly like Emacs does it. How this works is that ;; creates :. I have also keybound ; to check for the preceding text and if it is : then it will execute a macro that deletes and replaces with :=. The side effect of this is that if the cursor is placed at a point in the text where : is just behind the point, this macro will ALSO execute then. I think this is likely a fairly rare event and I have no other way to create this behavior, so I opted for this workaround.
  • ---- : Again I cannot duplicate this by checking the prior text because that would create issues if someone was just trying to make a custom length comment dash line. I created the --= as a replacement for the comment box.
  • == : Honestly I could create this one however it's kind of pointless. The == is not a VHDL operator and I'm not honestly certain why it's in Emacs vhdl-mode.

Snippets

Most snippets will execute from the keyword associated with them (i.e. 'entity' will fill out the beginning and ending structures and leave the cursor in the middle.) Each of these snippet words require hitting Tab afterwards to execute. This is just a list of the less obvious shortcuts. A full list of the snippets implemented may be found by selecting the Tools >> Snippets menu.

  • spro : Synchronous Process
  • cpro : Combinatorial Process
  • funcd : Produces a function specification/declaration
  • funcb : Produces a function with body.
  • procd : Produces a procedure specification/declaration
  • procb : Produces a procedure with body.
  • genmap : Produces a generic map association list, differentiated from a generic interface list.
  • portmap : Produces a port map association list, differentiated from a port interface list.
  • project : Active while editing a Sublime Text project file. Fills in local copies of the setting keys and instantiates a couple of example build systems.
  • And others... again please see the Snippets directory or the Tools >> Snippets menu for the complete list.

Miscellaneous Features

  • The insert header command uses several fields from the package settings. Please see above in Configuration for a list of the fields and types to edit to customize the header insertion.
  • The on-save event is trapped and will do a scan of the file, and by default look for -- Last update : in a VHDL file. If it finds this structure it will update the time and date on that line automatically (it removes that lines and replaces it). This pattern is configured through settings.
  • Most commands (save for snippets) will leave a trace in the ST3 console which may be useful for debugging. Any package message specific to this package will start with vhdl-mode:

Known Issues and Design Commentary

  • This is a work in progress however I've been eating my own dog food and it works fairly satisfactorily for me currently. I've thrown several code styles and files from other authors at it and tried to iron out the stranger bugs. However there are a lot of coding styles and I do not promise that the beautifier will work with every one of them. If there is an issue with a particular structure, I'm happy to get a sample and see if I can make it work.
  • The TextMate VHDL syntax supported non-matching identifiers in several locations. In order to get greater scope granularity, I had to sacrifice that feature in a few constructs because match captures do not persist through syntax scope set commands. More work can be done in identifying illegal identifiers in various locations however.
  • The syntax file was written with reference to the language definition in Designer's Guide to VHDL, 3rd Edition by Peter Ashenden. The language definition reference is in Appendix B, and library reference taken from Appendix A. Knowing how the language is structured may help understanding the syntax file and why it's done the way it is.
  • Designed to work with Sublime Text 3. It is unlikely to work with Sublime Text 2 (that is to say, I would be delighted if it did, however I have never used ST2 nor tested against it so your mileage may vary.)
  • I wrote my own comment routine for the region. This may not work the same way as ST3's own comment/uncommenter. I tried to keep the vhdl-mode behavior where it will region indent everything at the same column.
  • I have not tested this on Linux or Mac so I cannot tell how well it may work, or not, as the case may be. I would love to find out if there are any issues and happy to attempt to resolve them.
  • I did not create a snippet for everything under the sun. In vhdl-mode, the templates were one of my least used features. Generally I like the templates to cover large scale things that save a lot of typing. That is to say, there's no real need in my mind for every single keyword to have its own snippet. That being said, other packages have some of those things, and Sublime Text 3's snippet creation capability is simple, easy-to-use, and quite customizable. If anyone creates one they believe flows naturally from regular coding I'd be happy to evaluate it and include it with attribution.
  • There's no particularly graceful way to handle vhdl-mode's prompting for fields, for example, when creating an entity. Thus, some of these behaviors were broken up into several snippets. Typing entity <Tab> will form the starting and stopping entity structure, then place the cursor in the middle. Typing port <Tab> at this point will start a port interface list. In this way the flavor of the templating is retained but within a ST3 model. If I can find a way to handle a full prompt construction, I will try to implement it, but for now it's limited to snippet support.

Miscellaneous

The supported method for installing this package is through Package Control. It is possible to install this by cloning the repository directly. This method is not supported by me. However here are a few pointers:

  • The package must be installed in Sublime Text's Packages directory. In Windows, this is c:/Users/<name>/AppData/Roaming/Sublime Text/Packages.
  • VHDL Mode depends on the ruamel-yaml package that is a generically installed package. I believe it is obtained when Sublime Text first loads the package and tries to straighten out dependencies, but I don't promise this happens smoothly like it does when installing from Package Control.
  • The Github project is "VHDL-Mode". The package name is "VHDL Mode" (notice the space in lieu of the dash). You will need to make sure to clone to a directory name with this substitution made, or rename the directory afterwards. There are links to files within the package that requires this file being named correctly (and this is unavoidable -- there is no way to generically address the file.) Any other problems I cannot really help with. Good luck! (You could always install directly from Package Control and then replace the directory with your cloned version if you liked -- that might resolve most of the weirdnesses but no promises.)

Contributors

This is a new section and I wanted to acknowledge and thank folks who have helped out with fixes and testing. If anyone else has fixes or contributions, please feel free to open an issue at the Github repository and we can discuss it. If submitting a pull-request, please target the develop branch, as I keep the master branch for releases only.

  • Sven Goossens (Github: @Sv3n)
  • Stefan Lippuner (Github: @stefanlippuner)
  • Martin Barez (Github: @martinbarez)

Conclusion

I hope you find this Sublime Text package useful for coding in VHDL. The language is a passion of mine and it has been a great experience extending Sublime Text to work with it.

This package is offered with no warranty and no liability. It's free to use and distribute with any code, however I would appreciate attribution for my work if forking, modifying, or incorporating. Happy to work with other Sublime Text package authors as well.

MIT License

Copyright (c) 2017 Mark Norton

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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vhdl-mode's Issues

Syntax scoping error

Syntax for component seems broken if a few options are left out. I think they're mandatory in VHDL-2008, but clearly not for prior versions of the language -- or my reference did not mark these words as optional. Anyhow, the following does not scope correctly:

	component tacan_ident
		port (
			ARB             : in  std_logic;
			CE              : in  std_logic;
			clk_80          : in  std_logic;
			ident_en        : in  std_logic;
			ident_en_edge   : in  std_logic;
			tacan_mode      : in  std_logic_vector (6 downto 0);
			tacan_mode_edge : in  std_logic;
			id_P_trigger    : out std_logic;
			id_S_trigger    : out std_logic;
			id_window       : out std_logic
		);
	end component;

The problem seems to be the inclusion of the word is after the component identifier, and the inclusion of the component identifier in the end clause.

Small Lexing Error with Procedure Arguments

It looks like there's a parenthesis issue with subprogram parameters and parenthesis. Maybe I don't have my parenthetical group inside of a subprogram definition (though subprograms are difficult enough to identify already.). For example:

		write(L, string'("%% NOTE: @Time: "));

marks the second ) as erroneous, which makes me think that perhaps the first closing paren matched against the first opening paren instead of the second.

User Nice Things

I think I should probably include a Preferences >> Settings menu to get to the settings, but that will take some research to find out. Also commands aren't showing up in the command palette and I need to find out how to make that work.

Proper fix to stutter typing

It's possible to use an "insert characters" command in keybindings. This would fix the stutter typing COMPLETELY for => <= and :=.

	{
		"keys": [".", "."],
		"command": "insert",
		"args": {"characters": "=>"},
		"context": [{"key": "selector", "operand": "source.vhdl"}]
	},

Syntax Scope for Labels

I suspect that all labels should be scoped as entity.name.label.vhdl. I have several that take on the name of the substructure like entity.name.process.vhdl and while that's true, they are, at heart, still lexically the label.

Port copying error

Parser threw the following error when copying this port (autogenerated from HDL Designer's State Machine tool from the legacy design)

ENTITY MRB_trigger IS
   PORT( 
      CE            : IN     std_logic;
      MRB           : IN     std_logic;
      clk_80        : IN     std_logic;
      tacan_mode    : IN     std_logic_vector (6 DOWNTO 0);
      MRB_P_trigger : OUT    std_logic;
      MRB_S_trigger : OUT    std_logic;
      MRB_window    : OUT    std_logic;
      NRT_trigger   : OUT    std_logic
   );

Error created:

vhdl-mode: Interface beginning found.
vhdl-mode: Interface end found.
Traceback (most recent call last):
  File "C:\Program Files\Sublime Text 3\sublime_plugin.py", line 818, in run_
    return self.run(edit)
  File "C:\Users\mnorton\AppData\Roaming\Sublime Text 3\Packages\vhdl_mode\vhdl_mode.py", line 150, in run
    _interface.parse_block()
  File "C:\Users\mnorton\AppData\Roaming\Sublime Text 3\Packages\vhdl_mode\vhdl_lang.py", line 997, in parse_block
    self.strip_head_tail()
  File "C:\Users\mnorton\AppData\Roaming\Sublime Text 3\Packages\vhdl_mode\vhdl_lang.py", line 935, in strip_head_tail
    self.if_string = self.if_string[hs.end():ts.start()]
AttributeError: 'NoneType' object has no attribute 'start'

Alignment in Paste as Signal

When using paste as signal, the alignment seems to fail on the final line. A sample:

	-- Testbench signals
    signal clk               : std_logic;
    signal reset             : std_logic;
    signal ttimer_ext_rst    : std_logic;
    signal ttimer_ext_rst_en : std_logic;
    signal tick_timer        : std_logic_vector(31 downto 0);
    signal tick10_irq        : std_logic;
    signal ttimer_rst_irq : std_logic ;

Snippet for if-generate

This thing is kind of annoying to write out and it requires a label so might as well snippet it.

Syntax Priority Error

Example: Using an identifier named 'width' as a subprogram parameter will cause it to be scoped as:

vhdl-mode: source.vhdl meta.block.package.body.vhdl meta.block.function.specification.vhdl meta.group.interface.vhdl support.type.textio.vhdl 

Since it gets scoped this way, the text past it gets marked as invalid.illegal.identifier.vhdl

Refactoring/Organizing Code

Just setting this up as an issue. The amount of commands and code has grown quite large and it may be time to split these out into separate python modules.

Consider auto indenting settings additions

It would be nice to get automatic indent after some structures like "then" and so forth. Typing in this mode and having to hit tab a lot has a strange feel to it, so it's something Emacs vhdl-mode was likely doing automatically.

Lexing Error in Component Close

Component identifier at the close is not handled. This might be a VHDL-87/93 thing. Will have to check into it.

BAD

   component inbuf
      port (
         pad : in  std_ulogic;
         y   : out std_ulogic
      );
   end component;

Document Personal Settings

It would probably be a good idea to create a section of the README to document the settings file for the mode.

Scoping of attribute

There's an error in scoping attribute if no space after the signal name:

	attribute syn_keep of gated_echo_ptrig: signal is TRUE;

Will fail. The following passes:

	attribute syn_keep of gated_echo_ptrig : signal is TRUE;

Beautification Error

There's now a bug in beautification where a simple architecture ends up with an indented end statement. Need to run this one down.

Extra space after stutter

Just from a usage standpoint, probably want to insert the space following the symbol as well as the symbol. Feels better to type like that.

Keybind Context

I should probably make sure that all language specific keybinds have context for source code just to be a good community package developer.

Beautification of Package Error

I've got a situation where the final line of a package is indenting when it should not.

package system_build_info is 
    
    -- Firmware version decoder ring
    constant C_BUILD_VERSION : std_logic_vector(15 downto 0) := 
        std_logic_vector(to_unsigned(118, 16));
    
    constant C_BUILD_TIME_YEAR  : integer := $CURRENT_YEAR;
    constant C_BUILD_TIME_MONTH : integer := $CURRENT_MONTH;
    constant C_BUILD_TIME_DAY   : integer := $CURRENT_DAY; 
    
end package system_build_info;

Seems to beautify strangely. However a file that does not include those final 3 constants beautifies fine. May be something to do with the field replacement tokens I'm using there. Scope though on the next to final line is correct.

EDIT: Actually it happened once and I can't seem to duplicate it now. Very strange. Will have to keep an eye out for it.

Build Systems

It would be nice to create some default build system. Could create a basic make build, or basic Modelsim/Questasim build using vcom. Unfortunately this varies a LOT with tool system, so it'd basically be a template. Maybe could be coupled with a "create build system" command that would take relevant data from the project file?

Header Fields

The Copyright and Revisions fields in the header are kind of my-company specific. I should revise these and make them less specific.

Add in symbol definition capability

This is not strictly an Emacs VHDL Mode capability, but it is a Sublime capability and it seems like it'd be useful to get the symbol definitions working now that I have good scoping.

Package Declaration and Package Body Snippets

Might be nice to put in some basic snippets for these though I think the reason I didn't before was because it's basically package <identifier> is and end package <identifier>;. Still, feels like an oversight.

Implement VHDL vhdl-mode keybinds

Since there's a context that selects against a setting, it does let me create keybinds specifically for original Emacs vhdl-mode users that will be familiar (and faster) than the ones I created for default behavior.

vhdl_mode.py throws an error when loaded through Package Control

There is now a new error when loading the file through Package Control. The import statement doesn't import the util and lang modules correctly as it says there's no vhdl_mode.

Traceback (most recent call last):
  File "C:\Program Files\Sublime Text 3\sublime_plugin.py", line 109, in reload_plugin
    m = importlib.import_module(modulename)
  File "./python3.3/importlib/__init__.py", line 90, in import_module
  File "<frozen importlib._bootstrap>", line 1584, in _gcd_import
  File "<frozen importlib._bootstrap>", line 1565, in _find_and_load
  File "<frozen importlib._bootstrap>", line 1532, in _find_and_load_unlocked
  File "C:\Program Files\Sublime Text 3\sublime_plugin.py", line 915, in load_module
    exec(compile(source, source_path, 'exec'), mod.__dict__)
  File "vhdl_mode in C:\Users\mnorton\AppData\Roaming\Sublime Text 3\Installed Packages\VHDL Mode.sublime-package", line 16, in <module>
ImportError: No module named 'vhdl_mode'

Need to resolve this quickly.

README Markdown Error

When viewed on Package Control, the paragraphs with keybindings don't seem to render correctly. Suspect it needs another blank line or something.

Throws error on testbench creation

When copying an interface to a testbench, it throws the error:

vhdl-mode: Interface beginning found.
vhdl-mode: Interface end found.
vhdl-mode: No generics found
vhdl-mode: Inserted header template.
vhdl-mode: Created testbench from interface.
error: Error loading syntax file "Packages/vhdl_mode/Syntaxes/VHDL.tmLanguage": Unable to open Packages/vhdl_mode/Syntaxes/VHDL.tmLanguage

Not sure why it's doing that because I don't use that (I think -- will have to check that module).

Lexing Error in type declaration

The record construct is matching something badly as the following does not end the type

GOOD

   type SPI_DEVICE_RECORD is record
      data_size   : na_byte;
      start_index : na_byte;
      en_pattern  : lv_dword;
      clk_pattern : lv_dword;
      reverse     : boolean;
   end record;

BAD

   type SPI_DEVICE_ARRAY is array (MEM_ATTEN_INDEX to MEM_TEMP_INDEX) of SPI_DEVICE_RECORD;

Alignment of => in a case statement.

If the first statement after a with <choice> => contains a (others => '0') (or similar), the => symbol will misalign because there is no scope change from the with statement to the normal statements. Not sure this can be easily remedied.

Multiline enumerated type doesn't beautify correctly.

A structure like

    type T_STATES is
    (
        S1, 
        S2,
        S3,
        S4,
    );

will beautify with the first parenthesis indented, the contents double indented, and the closing double back-indented to line up with type. Doesn't seem to break anything else but might need a special rule similar to instantiations.

Add subprogram copying capability

This IS a VHDL Mode capability to be able to copy subprogram definition and paste as a declaration or body. I need to research to see if there are different commands than port copy.

Abstracting Beautification Rules

Going to be moving these rules out of vhdl_lang and into a YAML file. That will reduce the complexity of that method quite a lot at least in the data structure part and let the code focus on the actual beautification method. Then I can use sublime.load_resource('Packages/VHDL Mode/path-to-YAML') to get the contents of the file, and then yaml.safe_load(contents) and I have everything.

Will need to add a dependency for the ruamel YAML library as well for this.

Package with generic map does not scope correctly. Beautify errors

A structure like the following does not scope correctly. This is a VHDL-2008 construct.

package master_bfm is new work.avalon_bfm_pkg
    generic map
    (
      G_DATA_WIDTH  => 32,
      G_ADDR_WIDTH  => 10,
      G_BURST_WIDTH => 4
    );
  use work.master_bfm.all;
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use work.RandomPkg.all;
  
  
  entity timer_tb is
  end entity;

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