In this project I designed a system that shows DSP capabilities of FPGA solutions. The FPGA design consists of:
- Finite-state machine for configuration an audio codec via I2C.
- I2S receiver for acquiring data from the audio codec.
- 6-order low-pass IIR filter to demonstrate filtering capabilities of FPGA.
- 4096-point FFT megacore from Altera to get the signal spectrum.
- VGA module with video RAM to display the spectrum.
All modules are written by myself except FFT megacore.
The design is intended for Terasic DE2-115 board with Cyclone IV FPGA chip.
KEY[0] - reset
SW[2:0] - background color
SW[17] - 1: filter off, 0: filter on
SW[16] - mic left/right channel
VGA: VESA 1024x768@70 Hz
FFT range: 0 - 1/4 Fs
Fs: 48 828.125 Hz
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