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pdpu's Introduction

👋 Hi there, this is Qiong Li.

  • 🌱 I'm a graduate student at ICAIS Lab @ Nanjing University, majoring in Integrated Circuit Engineering.
  • 👀 I'm researching on Posit-based Hardware as well as its Applications in Deep Learning.
  • 🤔 I'm currently working on Integration of Posit format with RISC-V.
  • 🔭 My main coding language is Verilog/SystemVerilog, but I'm also familiar with C, Python, MATLAB, etc.
  • 💬 Ask me about ...

pdpu's People

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pdpu's Issues

Reg giving input

How to force the input for operand_a,operand_b packed array if I gave in any format it is providing error

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