- Supported boards:
- Tool Version
- Vivado 2020.2
In hw
folder
vivado -notrace -mode batch -source scripts/run.tcl
The block design is shown as below, The IP axis_test_pattern_0
generates stream packets with length 1024.
Program the board using the output *.bit
. Reboot the system on each time you program the FPGA.
The Windows 10 driver is located in driver
folder.
- Turn off the driver signature enforcement on Windows.
- Specify the driver file in Device Manager.
- Reboot.
Two applications are provided in app
folder. Refer to https://github.com/yiyaowen/xdma_driver_win for the source code.