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VSD Open On-Chip Clock Multiplier (PLL) on OSU180

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This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.


Contents

Introduction

The phase locked loop take in a signal to which it locks and can then output this signal from its own internal VCO. At first sight this may not appear particularly useful, but with a little ingenuity, it is possible to develop a large number of phase locked loop applications.

Block Diagram of PLL

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Literature review and architecture design theory points

  1. Design of Analog CMOS Integrated Circuits Behzad Razavi
  2. Design of CMOS Phase Locked Loops Behzad Razavi

Theory and Fundamental Concepts

  1. CMOS and Transistor Sizing
  2. Control System Feedback Loop
  3. IC Fab process
  4. Euler path

Setting up Linux Environment

Download the latest version of Virtual Box from the following link: https://www.virtualbox.org/ After installation it will look somewhat like this: image Download the Ubuntu Disk Image: https://ubuntu.com/download/desktop Create a new machine: image Follow the steps hereafter.

After complete installation the Ubuntu window looks like this: image

Installations

Git

Open terminal and run:

sudo apt-get install git

Then do:

git clone https://github.com/parasgidd/avsdpll_3v3.git

eSim

Install eSim and follow steps from here: https://esim.fossee.in/downloads

Magic

Run following Commands in the terminal: git clone git://opencircuitdesign.com/magic

cd magic
sudo ./configure
sudo make
sudo make install

Running eSim and Ngspice

eSim Schematic of inverter example

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Running Ngspice

cd /avsdpll_3v3/prelayout$
ngspice inv.cir

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Output Waveforms

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Prelayout

PFD Design

image image image

Charge Pump

image image image

VCO

image image image

freq_div

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PLL Prelayout

image image

Physical Design

Layout of Inverter

Run the following command to open Magic:

magic -T SCN6M_SUBM.10.tech

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Layout of PFD

image image image

Layout of VCO

image image image

Layout of FreqDiv2

image image image

Layout of FreqDiv8

image image image

Layout of mux21

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Final Layout of PLL

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Acknowlegment

I would like to thank Mr.Kunal Ghosh and Mr. Paras Gidd for the tutorial explained in the simplest way possible. It helped me to learn more about the PLL and layout design and simulations using Magic and Ngspice in a very easy and structured manner.

References

  1. https://www.vlsisystemdesign.com/registration/
  2. https://vsdiat.com/
  3. https://github.com/parasgidd/avsdpll_3v3
  4. https://www.virtualbox.org/
  5. http://opencircuitdesign.com/magic/download.html
  6. https://esim.fossee.in/downloads
  7. https://www.electronics-notes.com/articles/radio/pll-phase-locked-loop/tutorial-primer-basics.php

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