VSD Open On-Chip Clock Multiplier (PLL) on OSU180
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
Contents
- Introduction
- Block Diagram of PLL
- Literature review and architecture design theory points
- Theory and Fundamental Concepts
- Setting up Linux Environment
- Installations
- Running eSim and Ngspice
- Prelayout
- Physical Design
- Acknowlegment
- References
Introduction
The phase locked loop take in a signal to which it locks and can then output this signal from its own internal VCO. At first sight this may not appear particularly useful, but with a little ingenuity, it is possible to develop a large number of phase locked loop applications.
Block Diagram of PLL
Literature review and architecture design theory points
- Design of Analog CMOS Integrated Circuits Behzad Razavi
- Design of CMOS Phase Locked Loops Behzad Razavi
Theory and Fundamental Concepts
- CMOS and Transistor Sizing
- Control System Feedback Loop
- IC Fab process
- Euler path
Setting up Linux Environment
Download the latest version of Virtual Box from the following link:
https://www.virtualbox.org/
After installation it will look somewhat like this:
Download the Ubuntu Disk Image:
https://ubuntu.com/download/desktop
Create a new machine:
Follow the steps hereafter.
After complete installation the Ubuntu window looks like this:
Installations
Git
Open terminal and run:
sudo apt-get install git
Then do:
git clone https://github.com/parasgidd/avsdpll_3v3.git
eSim
Install eSim and follow steps from here: https://esim.fossee.in/downloads
Magic
Run following Commands in the terminal: git clone git://opencircuitdesign.com/magic
cd magic
sudo ./configure
sudo make
sudo make install
Running eSim and Ngspice
eSim Schematic of inverter example
Running Ngspice
cd /avsdpll_3v3/prelayout$
ngspice inv.cir
Output Waveforms
Prelayout
PFD Design
Charge Pump
VCO
freq_div
PLL Prelayout
Physical Design
Layout of Inverter
Run the following command to open Magic:
magic -T SCN6M_SUBM.10.tech
Layout of PFD
Layout of VCO
Layout of FreqDiv2
Layout of FreqDiv8
Layout of mux21
Final Layout of PLL
Acknowlegment
I would like to thank Mr.Kunal Ghosh and Mr. Paras Gidd for the tutorial explained in the simplest way possible. It helped me to learn more about the PLL and layout design and simulations using Magic and Ngspice in a very easy and structured manner.
References
- https://www.vlsisystemdesign.com/registration/
- https://vsdiat.com/
- https://github.com/parasgidd/avsdpll_3v3
- https://www.virtualbox.org/
- http://opencircuitdesign.com/magic/download.html
- https://esim.fossee.in/downloads
- https://www.electronics-notes.com/articles/radio/pll-phase-locked-loop/tutorial-primer-basics.php