princetonuniversity / prga Goto Github PK

It would be good to link to https://prga.rtfd.io in the README.md incase people are looking at a checkout rather than the GitHub interface.

ding@ding-desktop:~/PyFPGA/prga$ sudo ./envscr/install
[INFO] PyFPGA install ......
[INFO] Using 'git': /usr/bin/git
[INFO] Using 'make': /usr/bin/make
[INFO] Using 'cmake': /usr/bin/cmake
[INFO] Using 'gcc': /usr/bin/gcc
[INFO] Locally-installed 'pyenv' found. Updating 'pyenv'
HEAD 目前位于 4ce52bd3 2.0.0-rc1
[INFO] 'pyenv' updated
[INFO] Activating locally-installed 'pyenv'
[INFO] 'pyenv' activated
[INFO] Installing Python 3.8.2 with 'pyenv'
[INFO] Downloading html .web Files....
Downloading Python-3.8.2.tar.xz...
-> https://www.python.org/ftp/python/3.8.2/Python-3.8.2.tar.xz
Installing Python-3.8.2...

BUILD FAILED (Ubuntu 18.04 using python-build 2.0.0-rc1)

Inspect or clean up the working tree at /tmp/python-build.20210729192017.18966
Results logged to /tmp/python-build.20210729192017.18966.log

Last 10 log lines:
File "/tmp/python-build.20210729192017.18966/Python-3.8.2/Lib/ensurepip/init.py", line 119, in _bootstrap
return _run_pip(args + [p[0] for p in _PROJECTS], additional_paths)
File "/tmp/python-build.20210729192017.18966/Python-3.8.2/Lib/ensurepip/init.py", line 27, in _run_pip
import pip._internal
File "", line 241, in load_module
File "", line 709, in _get_module_code
File "", line 570, in _get_data
zipimport.ZipImportError: can't decompress data; zlib not available
Makefile:1186: recipe for target 'install' failed
make: *** [install] Error 1
ding@ding-desktop:~/PyFPGA/prga$

Extend magic programming circuitry to generate a Verilog file for verifying bitstream loading results.

Double check:

• Reset strategy
• Behavioral simulation/gatesim compatibility
• Eliminate X's

Specific issues:

• cfg_e, cfg_we, cfg_rst delivery and synchronization

Hello,
may i ask, if there is a way that i can get the bitstream file after running the design?

Python 2 is dead. Python 3 should be supported. It's pretty easy to support both 2.7 and 3 these days, but just supporting 3 is another option.

The End Of Life date (EOL, sunset date) for Python 2.7 has been moved five years into the future, to 2020.

Currently each configuration circuitry type generates its own FASM format. Instead, we should use a generic FASM format, and let the bitstream generator figure out how to translate that to binary bitstream.

The generic FASM format could use the module hierarchy as the FASM feature name. For multi-modal primitives, we can use something like prefix.primitive:mode.suffix

SystemVerilog offers many great features that simplify/clarify code, and more importantly, enhance testability (assertions, etc.)

Currently the entrypoint of PRGA is *.new_context, and file rendering engine is created by *.new_renderer, in which * is a configuration circuitry type (magic, scanchain, or pktchain). This forces the selection of configuration circuitry types before describing the architecture. It also makes *.InsertProgCircuitry pass error-prone.

We should instead start with a generic context, and then leave the configuration circuitry selection to later steps. We can use magic as the default configuration circuitry type, which is not real, but helps with debugging the FPGA architecture at the abstract level. Then, the context may be "materialize" to a specific configuration circuitry type.

For example:

ctx = Context()

ctx.create_global(...)
ctx.create_segment(...)
ctx.build_logic_block(...)
...

flow = Flow(
    Translation(),
    SwitchPathAnnotation(),
    InsertProgCircuitry(),  # calls Magic._InsertProgCircuitry under the hood
    VPRArchGeneration("vpr/arch.xml"),
    VPR_RRG_Generation("vpr/rrg.xml"),
    VerilogCollection('rtl'),
    YosysScriptsCollection(r, "syn"),
    ).run(ctx)

# Until now everything is using `magic` as the configuration circuitry type.

ctx = Scanchain.materialize(ctx)

flow = Flow(
    Translation(),
    SwitchPathAnnotation(),
    InsertProgCircuitry(),  # calls Scanchain._InsertProgCircuitry under the hood
    VPRArchGeneration("vpr/arch.xml"),
    VPR_RRG_Generation("vpr/rrg.xml"),
    VerilogCollection('rtl'),
    YosysScriptsCollection(r, "syn"),
    ).run(ctx)

At this moment the generated VPR model adds some fake delay. I would like to update with more realistic dealy. What are the steps for that? For example, right now I got a more accurate delay from the layout of the RTL model, and want to update the PRGA for that.

I got your source code from here and install all modules "YOYS, VTR, PRGA" without any error, and done all the process which indicated in the documentation.

cd /path/to/prga/
./envscr/install

then I built an FPGA "tiny/k4/N2_8x8" without any error, but during implementation and simulation I got the following error :

Could anyone help me solve this issue?

Thanks in advance.

• Ubuntu 20.04.1 LTS 5.4.0-48-generic
• GNU Make 4.2.1
• Clang version 10.0.0-4ubuntu1
• Python 3.8.2
• gcc version 9.3.0

# Re-activate virtual environment if you exited or started a new terminal session
#   cd /path/to/prga/                           # cd to the root
#   ./envscr/activate                           # activate the virtual environment
cd examples/target/bcd2bin/tiny_k4_N2_8x8   # choose one design and one FPGA
make                                        # run all the way to verification

Output of make :

make -f Makefile.sim
make[1]: Entering directory '/home/john/work/python/john/prga/examples/target/bcd2bin/tiny_k4_N2_8x8'
vpr /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml bcd2bin.blif --circuit_format eblif --pack --net_file bcd2bin.net --constant_net_method route \
	| tee bcd2bin.pack.log
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+2c288b884
Revision: v8.0.0-2839-g2c288b884
Compiled: 2020-09-24T13:25:10
Compiler: GNU 9.3.0 on Linux-5.4.0-48-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
[email protected]
This is free open source code under MIT license.

VPR was run with the following command-line:
vpr /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml bcd2bin.blif --circuit_format eblif --pack --net_file bcd2bin.net --constant_net_method route


Architecture file: /home/john/work/python/john/prga/examples/fpga/tiny/k4_N2_8x8/vpr/arch.xml
Circuit name: bcd2bin

# Loading Architecture Description
# Loading Architecture Description took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)
# Building complex block graph
# Building complex block graph took 0.00 seconds (max_rss 14.2 MiB, delta_rss +0.0 MiB)
Error 1: 
Type: Blif file
File: bcd2bin.blif
Line: 158
Message: Failed to find matching architecture model for '$_SDFF_PP0_'

# Load circuit
Found constant-zero generator '$false'
Found constant-one generator '$true'
Found constant-zero generator '$undef'
# Load circuit took 0.00 seconds (max_rss 16.1 MiB, delta_rss +1.9 MiB)
The entire flow of VPR took 0.00 seconds (max_rss 16.1 MiB)
make[1]: *** [Makefile.sim:201: bcd2bin.net] Error 1
make[1]: Leaving directory '/home/john/work/python/john/prga/examples/target/bcd2bin/tiny_k4_N2_8x8'
make: *** [../Makefile.in:27: all] Error 2

Hi, while building PRGA on Ubuntu 20.04, an error is encountered saying pyenv is not choosing the correct python version, then at a later stage, the installation script reports "Locking Failed" and crashes in a python command /home/jcma/prga/prga.py/.venv/bin/python /home/jcma/.local/lib/python2.7/site-packages/pipenv/patched/notpip install --ignore-installed --no-user --prefix /tmp/pip-build-env-gksjbwmb/overlay --no-warn-script-location --no-binary :none: --only-bi nary :none: -i https://pypi.org/simple -- setuptools wheel setuptools_scm

Also attached the full log.
log.txt

Hello,
i want to add a custom verilog module, but there's no tutorial showing me how to do that.
can you give me some advice?

Hi, I came across PRGA topic while searching for open source FPGA and EDA tools, looks really amazing; I am very new to these open-source tools and Python. While building k4_N2_8x8 as per docs/source/intro.rst (shorturl.at/iopAM), I am facing following error.

python build.py
Traceback (most recent call last):
File "build.py", line 3, in
from prga.api.context import *
ModuleNotFoundError: No module named 'prga'
make: *** [../../Makefile.in:10: ctx.pickled] Error 1

Installation was successful and before running the MAKE, ./envscr/activate was also run without any issues.

I am missing something extremely important? Can anyone please help?

Hello,

i try to generate a new custom block called "hard_logic_block" (similar as a DSP-block), which has the same level as club-block from the hierarchy , but it shows me an error.

Besides, i still wanna ask something about Bitstream. I think the FPGA is successfully generated, but i can't find the bitstream file in the output files.

It would be good if you could get from the prga documentation to the github repository really easily.

I suggest the following;

• Add a link to the github repo on the navigation section.
• Add a link to the github repo on the front page.
• Enable the "edit this page on github" functionality of rtd. (See https://github.com/SymbiFlow/prjxray/blob/master/docs/conf.py#L67-L75 for an example).

When compiling under msys2, I encountered the following error:

[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdApi.c.obj
[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdAuto.c.obj
[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdFlag.c.obj
In file included from D:/prga/vtr/abc/src/base/cmd/cmdAuto.c:33:
D:/prga/vtr/abc/lib/pthread.h:308:8: error: redefinition of 'struct timespec'
308 | struct timespec {
| ^~~~~~~~
In file included from C:/msys64/mingw64/include/time.h:25,
from D:/prga/vtr/abc/src/misc/util/abc_global.h:72,
from D:/prga/vtr/abc/src/base/cmd/cmdAuto.c:25:
C:/msys64/mingw64/include/sys/timeb.h:101:8: note: originally defined here
101 | struct timespec {
| ^~~~~~~~
[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdHist.c.obj
make[3]: *** [abc/CMakeFiles/libabc.dir/build.make:1592: abc/CMakeFiles/libabc.dir/src/base/cmd/cmdAuto.c.obj] Error 1
make[3]: *** Waiting for unfinished jobs....
[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdLoad.c.obj
[ 11%] Building C object abc/CMakeFiles/libabc.dir/src/base/cmd/cmdPlugin.c.obj
make[2]: *** [CMakeFiles/Makefile2:935: abc/CMakeFiles/libabc.dir/all] Error 2
make[1]: *** [Makefile:146: all] Error 2
make: *** [Makefile:82: all] Error 2

Administrator@WIN-C4T6417PL75 MINGW64 /d/prga

How should this problem be eliminated?

It would make it clear what the license this code is under and provide you a nice badge on the github repo. See example;

This is harder than it seems. The reasons is we need to be able to write to the RAM during programming, which means we need to be able to write to the RAM in two different clocks (but in different periods). Also complicates bitstream generation.

I am using the latest release of PRGA. However, while trying to generate a small FPGA faced the following error:
'IOBlock' object has no attribute 'is_io_block'

Is there any workaround or I am missing something.