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MIPS:- Microprocessor without Interlocked Pipelined Stages is a 32 bit RISC ISA. In this project, I have implemented a 5 stage Pipelined Processor processing various instruction at a single clock Cycle. Only a small set of instruction is implemented. Characteristics:

1. 32, 32 bit GPRs,R0-R31
2. A special purpose 32 bit PC
3. No Flags Registers
4. Addressing modes- Register, immediate and register indexed
5. Only load and store instructions can access memory
6. Memory word size is 32 bits and is word addressable.
7. One Read and two Write Port Instruction Subset:
8. Load and Store Instructions
9. Arithmetic and logic instruction(only register operands and Immediate operand)
10. ADD R1,R2,R0 // R1 = R2 + 0
11. SUB R12,R10,R8 // R12 = R10 – R8
12. AND R20,R1,R5 // R20 = R1 & R5
13. OR R11,R5,R6 // R11 = R5 | R6
14. MUL R5,R6,R7 // R5 = R6 * R7
15. SLT R5,R11,R12
16. ADDI R1,R2,25
17. SUBI R5,R1,150
18. SLTI R2,R10,10
19. Branch Instructions Academic Report
20. BEQZ R1,Loop
21. BNEQZ R5,Label
22. Miscellaneous Instruction
23. HLT

To know more please refer this link:-" https://drive.google.com/file/d/1M3elHzYxrQsOYWBfFgzjtk69ndPGDvMS/view?usp=sharing"