Motivation

When @SihaoLiu and I was preparing for the MICRO tutorial, we realized that our current ISA design is:

1. Complicated: Too many reserved slots are occupied, and
2. Broken: Violates the semantics of Chipyard convention. The FUNCT3 opcode cannot be randomly given, it depends on the number of registers communicated between the host and the accelerator.

FUNCT3 is a 3-bit binary number composed by xs0, xs1, and xd, which indicates the number of registers that receive/send between host and accelerator. Moreover, xs1 cannot be 1 alone, since the accelerator can only receive value from host Rs1.

Proposed Solution

Configuration Instructions

All the configuration instructions can be merged into one.

I propose we have a 64-register file in the accelerator and each register is dedicated to its semantics to avoid register allocation. To set the register we only need an S-type instruction. The 12-bit imm value will be shared by two 6-bit register indices --- low half for rs1 and high half for rs2. The register[0] is reserved for an 0-register like x0, when we only want to set one register.

imm[11:5] | rs1 | rs2 | func3 | imm[4:0] | opcode

TODO: We need to decide the semantics of each register. It takes a while to collect the intrinsics, and assign them to a slot in the register file.

Synchronization Instructions

Synchronized instructions like SS_WAIT_ALL and SS_RECV should have xd=1 set.

Events

Events include everything asynchronous, like barriers and stream instantiation.
We just use the imm as a flag of event and we do not want to send/receive any data?