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ghidra-upd77016-lang's Introduction

A SLEIGH processor spec for Ghidra for the NEC μPD77210 digital signal processor.

Installation

This repository should be placed within the Ghidra install as the folder Ghidra/Processors/uPD77016, such that Ghidra/Processors/uPD77016/data is the path to the data folder. Ghidra should automatically add it to the available processor list on its next start, and compile the files when it is first used.

Manuals

The μPD77210 Family Digital Signal Processor Architecture manual covers registers for μPD77210 and μPD77213, but refers to the μPD77016 Family Digital Signal Processor Instructions manual for the instruction set, also covering the μPD77015, μPD77016, μPD77017, μPD77018, μPD77018A, μPD77019, μPD77110, μPD77111, μPD77112, μPD77113 and μPD77114. The primary goal of this project is to cover the uPD77210, but it should theoretically be usable for any of these.

Unfortunately, these manuals don't talk about the encoding of instructions in detail. Appendix A of the μPD77016 manual shows some information about instruction fields, and gives a list of values associated with the fields, but doesn't actually say what the numeric value corresponding to each entry is. In practice, it seems like most of them are just in order, but a few of them have fewer values than could fit. This EEVblog forum thread provides one user's guesses at what they should be (which seem to be correct based on actual binaries).

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ghidra-upd77016-lang's Issues

Register numbering for dest1/source2

This is absolutely great work! Well done.

Just one issue I've spotted. and it's with dest1 in fig A-6. I think dmy is 0x14, and not 0x11?

I have this code...

0E32: 3C800000 dp0 = r1l
0E33: 3C880000 dp4 = r1l
0E34: 38100001 dn0 = 0x0001
0E35: 38180001 dn4 = 0x0001
0E36: 38200FFF dmx = 0x0FFF
0E37: 38280FFF dmy = 0x0FFF

...and it makes absolutely zero sense to be setting STK here, as it disassembles in Ghidra...

       inst:0e32 00 00 80 3c     MOV        DP0 = R1L 
       inst:0e33 00 00 88 3c     MOV        DP4 = R1L 
       inst:0e34 01 00 10 38     LDI        DN0 = 0x1 
       inst:0e35 01 00 18 38     LDI        DN4 = 0x1 
       inst:0e36 ff 0f 20 38     LDI        DMX = 0xfff 
       inst:0e37 ff 0f 28 38     LDI        STK = 0xfff 

Which implies dest1/source2 in fig A-5 is also wrong. And that appears to be confirmed by this code which, from context, is clearly disabling/enabling the HOST IN IRQ in the SR...

0382: 3D410000 r2l = sr
0383: 5B480100 r2 = r2 | 0x0100					;disable HI_IRQ
0384: 3D400000 sr = r2l
....
03A7: 3DC10000 r3l = sr
03A8: 5A6CFEFF r3 = r3 & 0xFEFF					;enable HI_IRQ
03A9: 3DC00000 sr = r3l

...but we get this in Ghidra...

       inst:0382 00 00 41 3d     MOV        R2L = DP0 
       inst:0383 00 01 48 5b     IOR        R2 = R2 | 0x100 
       inst:0384 00 00 40 3d     MOV        DP0 = R2L 
....
       inst:03a7 00 00 c1 3d     MOV        R3L = DP0 
       inst:03a8 ff fe 6c 5a     IAND       R3 = R3 & 0xfeff 
       inst:03a9 00 00 c0 3d     MOV        DP0 = R3L 

Seems to me the register mappings for dest1/source1 contain 2 completely separate sets of registers, because index 0 maps to both dp0 and sr (if you assume 5 bits)?

Which set of registers is accessed depends on if the instruction is conditional (accesses the various pointer registers), or unconditional (accesses system registers). Either that or you need to consider bit 22 is included as part of the register number for a total of 6 bits?

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