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Labs of the Reconfigurable Computing course, University of Aveiro

VHDL 78.15% Pascal 0.01% Tcl 0.08% Batchfile 0.01% C 2.60% HTML 0.03% JavaScript 0.01% Shell 0.01% PureBasic 0.01% Coq 15.56% Verilog 1.22% SystemVerilog 0.30% C++ 0.62% V 1.14% Makefile 0.02% Scala 0.10% CartoCSS 0.01% Assembly 0.15% Python 0.01%
vhdl reconfigurable-computing xilinx fpga fpga-soc axi

cr-labs's Introduction

Reconfigurable Computing

MSc in Computer and Telematics Engineering | University of Aveiro

pedrovt 2020


Labs

  • Lab 1 : Familiarization with the Xilinx Vivado IDE and the Digilent Nexys 4 kit
  • Lab 2 : Construction of a module to control the 7-segment displays (multiplexed) of the Digilent Nexys 4 kit
  • Lab 3 : Construction of a mm.ss (countdown timer) hour counter with countdown, entirely in hardware
  • Lab 4 : Software implementation of an mm.ss hour counter with countdown timer
  • Lab 5 : Implementation in software + specialized hardware of a countdown timer with countdown (mm.ss)
  • Lab 6 : Software implementation to be performed on an RTOS + specialized hardware of a countdown timer with countdown (mm.ss)
  • Lab 7 : Implementation of specialized hardware coprocessors with AXI stream interfaces (master and slave) to accelerate "reverse endianess" and "population count" operations
  • Lab 8 : Use of DMA transfers between memory and a coprocessor / peripheral with AXI4 stream interface
  • Lab 9 : Systems with multiple clock domains

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