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Right now, designs containing this aurora kernel can only be verified in hardware, which results in a very tedious development process. One possible solution would be to create a drop-in replacement of the aurora core which uses named pipes instead of the QSFP ports.

Using for example two lanes per aurora core could enable more network typologies, as one QSFP port could be connected in two different directions. This is just idea with no guarantees that it is possible.

The smallest message size which can be configured in the example design is 64 bytes, which is the width of the FIFO. The aurora core itself sends messages in chunks of 32 bytes. This can be reached with setting the keep bits in a single transfer to half of the bytes. This should flush the datawidth converter and lead to a single transfer of the aurora core. With some small changes to the issue kernel, it could be verified, if this is really the case.

The CRC counter is a module, which counts the number of frames and the number of frames with errors. The correctness of the module can be verified with the integrated logic analyzer. But when passing the value out with the AXI Control module, it is just zero. This needs to be investigated. It may has something to do with constraints on which register addresses can be really be read.

The design is only tested on the U280 Alveo card. Verify that it also works on other boards.