Comments (5)
The L1 I/D caches are part of the core rtl.
This is the spec for the core interface:
A2L2 Spec
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@openpowerwtf Is A2 designed by full custom?
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No, I don't think any of the random logic was custom.
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thanks
from a2i.
Don't forget - BlueGene ran at a slow frequency to balance system power/perf. Would have to synthesize to real technology today to see what the critical paths are; very likely some are around arrays.
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