Comments (2)
openpowerwtf
commented on August 30, 2024
What do you mean by 'address space'? Do you mean address translation, or how software uses the memory space?
from a2i.
Grubby-CPU
commented on August 30, 2024
I mean in Power servers, which memory space is assigned to DDR and which memory space is assigned to I/O devices. For example, 0 - 2GB is assigned to I/O, 2GB-4GB is assigned to DRAM, 4GB-16GB is reserved and 16GB-32 GB is assigned to I/O and so on. Any public references?
from a2i.
Related Issues (20)
- The RAW/WAW dependency check in iuq_fxu_dep.vhdl HOT 1
- Questions regarding testing A2I with Coremark on FPGA without OS HOT 5
- Problem in simulation of the a2l2_axi.vhdl file HOT 5
- Any hints about the ignore_flush_is0 signal HOT 1
- Question regarding the address map of A2i core HOT 8
- Question regarding how to drive signal ac_an_req_ld_xfr_len and ac_an_req_ttype (hwsync) of a2l2_axi.vhdl in simulation. HOT 1
- Unbalanced instruction fetch latency and instruction fetch width HOT 6
- A design drawback of thread issue selection?
- Assistance Required in building A2I core in Vivado Windows HOT 1
- How to deal with wrong target address prediction of link stack HOT 1
- Why choosing ex4 to deal with interrupt and exception HOT 2
- How to fetch later instructions if a branch instrution is met HOT 1
- build and run videos are no longer available HOT 1
- Error happens when two threads co-execute together HOT 16
- About the payload bits of msgsnd instruction HOT 2
- About the memory consistency model in A2
- Why msgclr does not set UsesSPR in iuq_fxu_decode.vhdl
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