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View Code? Open in Web Editor NEWRTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
License: Other
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
License: Other
Hi,
I work at BSC, we are integrating the cache in a core and have an issue with the simulations (using Verilator 5.010) of the core using the cache. The output is as follows:
[0] %Error: hpdcache_rrarb.sv:117: Assertion failed in TOP.veri_top.DUT.dcache.hpdcache_ctrl_i.st0_arb_i.gnt_q_exactly_one_requester: arbiter: grant state is not one-hot
%Error: rtl/dcache/rtl/src/common/hpdcache_rrarb.sv:117: Verilog $stop
Aborting...
The issue is because at the start of the simulation, in file hpdcache_rrarb.sv
, signal gnt_q
is 0 (since verilator is a 2-state simulator) and so it fails the assert.
There is nothing wrong with the behavior itself, since the assert itself is correct, and gnt_q
will be correct as soon as the reset signal is applied. The problem lies within the simulation setup, i.e. the initial value of gnt_q
being set to 0. I suggest adding something such as:
`ifdef VERILATOR
initial begin
gnt_q = {1'b1, {N-1{1'b0}}};
end
`endif
We have tested this internally and have had no problems. If needed I can submit a pull request.
Thanks,
Arnau.
Hello! I am Noelia Oliete.
During the integration of the HPDC and OpenPiton for the GSoC'23, I detected that the refills don't work when the configurable parameter HPDCACHE_ACCESS_WORDS is equal to 1 or to HPDCACHE_CL_WORDS (Now I am using 16B/cache line).
End index -1 of part-select into 'word_i' is out of bounds.
This error is due to the next line since we cannot index word_i with "[0 +:0]".
off = hpdcache_uint'(word_i[0 +: $clog2(HPDCACHE_ACCESS_WORDS)]);
To solve this compilation error, I would like to propose the following code (it works for Verilator and Questa/Modelsim). Notice that when HPDCACHE_ACCESS_WORDS, the new parameter HPDCACHE_ACCESS_WORDS_LOG2 takes the value 1 to avoid a compilation error in Verilator.
function automatic hpdcache_data_row_enable_t hpdcache_compute_data_ram_cs(
input hpdcache_req_size_t size_i,
input hpdcache_word_t word_i);
localparam int unsigned HPDCACHE_ACCESS_WORDS_LOG2 = (HPDCACHE_ACCESS_WORDS==1) ? 1 : $clog2(HPDCACHE_ACCESS_WORDS);
hpdcache_data_row_enable_t ret;
hpdcache_uint32 off;
case (size_i)
3'h0,
3'h1,
3'h2,
3'h3: ret = hpdcache_data_row_enable_t'({1{1'b1}});
3'h4: ret = hpdcache_data_row_enable_t'({2{1'b1}});
3'h5: ret = hpdcache_data_row_enable_t'({4{1'b1}});
default: ret = hpdcache_data_row_enable_t'({8{1'b1}});
endcase
off = (HPDCACHE_ACCESS_WORDS==1) ? hpdcache_uint'(0) : hpdcache_uint'(word_i[0 +: HPDCACHE_ACCESS_WORDS_LOG2]);
return hpdcache_data_row_enable_t'(ret << off);
endfunction
Hope this could help.
Thank you,
Noelia.
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