I am currently learning Verilog and SystemVerilog for IC design and verification.
Here is my CV
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๐ M.S. Mechanical Engineering (Program of System Control)
๐ 2021 - 2023
๐ซ National Taiwan University - Taipei, Taiwan -
๐ B.S. Electrical Engineering (Double Major)
๐ 2018 - 2021
๐ซ National Taiwan Normal University - Taipei, Taiwan -
๐ B.S. Mechatronic Engineering (Main Major)
๐ 2017 - 2021
๐ซ National Taiwan Normal University - Taipei, Taiwan
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๐ฑ My GitHub Data
๐ฆ 6.8 MB Used in GitHub's Storage
๐ 200 Contributions in the Year 2024
๐ผ Opted to Hire
๐ 46 Public Repositories
๐ 24 Private Repositories
๐ This Week I Spent My Time On
๐๏ธ Time Zone: Asia/Taipei
๐ฌ Programming Languages:
No Activity Tracked This Week
๐ฅ Editors:
No Activity Tracked This Week
๐ฑโ๐ป Projects:
No Activity Tracked This Week
๐ป Operating System:
No Activity Tracked This Week
I Mostly Code in Python
Python 25 repos โโโโโโโโโโโโโโโโโโโโโโโโโ 35.71 %
C++ 24 repos โโโโโโโโโโโโโโโโโโโโโโโโโ 34.29 %
C 7 repos โโโโโโโโโโโโโโโโโโโโโโโโโ 10.00 %
Verilog 4 repos โโโโโโโโโโโโโโโโโโโโโโโโโ 05.71 %
SystemVerilog 1 repo โโโโโโโโโโโโโโโโโโโโโโโโโ 01.43 %
Last Updated on 26/05/2024 18:39:32 UTC