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scapy

Scapy: the Python-based interactive packet manipulation program & library. Supports Python 2 & Python 3.

shadowsocks

A fast tunnel proxy that helps you bypass firewalls

simple_reg_model

System verilog register model for uvm testbenches.

svaunit

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

svunit

systemverilogreference

training labs and examples

thesisuestc

ThesisUESTC-电子科技大学毕业论文模板

uestcthesis

电子科技大学毕设设计论文LaTeX模板

usb-test-suite-build

Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores

uvm

UVM examples and projects

uvm-apb_ral

This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.

uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

uvm-verification-testbench-for-simplebus

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

v2ray-core

A platform for building proxies to bypass network restrictions.

v2ray-guide

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-caches

Various caches written in Verilog-HDL

verilog-ethernet

Verilog Ethernet components for FPGA implementation

wujian100_open

IC design and development should be faster，simpler and more reliable

yuu_register_productor

UVM register utility generation by inputting xls table