new metrics that are used in the literature: mean error distance (med), mean relative error distance (mred), error rate (er), mean squared error distance (msed)

It can happen that verilog files generated from different methods (such as MECALS) do not contain the correct module name, which consequently breaks the parsing of the information in the files. I developed a quick solution to specify the models correctly from their names.

I called the file 'specify_module.py' for now.

import os
import sys
from tempfile import mkstemp
from shutil import move, copymode

verilog_path = sys.argv[1]

input_list = os.listdir(verilog_path)

for file in input_list:
    subst = file[:file.rfind('.')]
    file_path = f'{verilog_path}/{file}'
    fh, abs_path = mkstemp()
    with os.fdopen(fh,'w') as new_file:
        with open(file_path) as old_file:
            for line in old_file:
                if 'module' in line and 'endmodule' not in line:
                    splt = line.split()
                    second = splt[1]
                    new_file.write(line.replace(second, subst))
                else:
                    new_file.write(line)
    copymode(file_path, abs_path)
    os.remove(file_path)
    move(abs_path, file_path)

The code simply requires the path to where the verilogs are saved and will update all the existing files with the correct module name.

Example use case:

$ python3 specify_module.py [path-to-verilogs]

will setup the files correctly.

Given that we have now used the verilog checker to validate circuits with their expected ET, we would like to get information such as area, power and delay in order to compare them with other circuits.
The idea is to add a feature to this tool that, given a specific semiconductor technology (which dictates the parameters we are looking for) and a circuit, would return the information we need to compare the performance of synthesized circuits.