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perfect6502, a MOS 6502 CPU emulator that performs a simulation of the original NMOS 6502 netlist

License: MIT License

Makefile 0.19% C 55.52% C++ 0.03% Objective-C 44.27%

perfect6502's Introduction

perfect6502

perfect6502 is a MOS 6502 CPU emulator that performs a simulation of the original NMOS 6502 netlist that was extracted by the visual6502.org project.

Consequently, perfect6502 is

perfect: It is not a reimplementation of the 6502, but a simulation of the original transistors. Its complete behavior, its internal state and its outputs are half-cycle exact.
slow: Even though perfect6502 is highly optimized C code, achieves only 1/30 of the speed of a 1 MHz 6502 on a high-end CPU of 2020.

perfect6502 is useful for

understanding and reverse engineering the 6502
debugging 6502 emulators by running them side by side with perfect6502

Usage

As a demonstration and as a performance/regression test, perfect6502 is hooked up to Commodore BASIC (cbmbasic).

You can compile the project with

$ make

and run it with

$ cbmbasic/cbmbasic

You should get the following output:

	**** COMMODORE 64 BASIC V2 ****

 64K RAM SYSTEM  38911 BASIC BYTES FREE

READY.

Benchmarking

You can use the UNIX time tool to measure the performance of the emulator. Run time cbmbasic/cbmbasic and press Ctrl+C once it has reached READY. – the "user" time is the effective time that was required to reach character input. On a 1 MHz 6502, this takes 0.05 sec.

Credits

perfect6502 is is written by Michael Steil and derived from the JavaScript visual6502 implementation by Greg James, Brian Silverman and Barry Silverman.

Contributing

Further performance optimizations are gladly accepted.

perfect6502's People

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perfect6502's Issues

Warnings and a link error

I get a lot of warnings with gcc 9 which break the compilation with -Werror:

netlist_sim.c: In function ‘getGroupValue’:
netlist_sim.c:390:1: error: control reaches end of non-void function [-Wreturn-type]
  390 | }
      | ^

cbmbasic/runtime.c: In function ‘LOAD’:
cbmbasic/runtime.c:558:17: error: variable ‘savedbyte’ set but not used [-Wunused-but-set-variable]
  558 |   unsigned char savedbyte;
      |                 ^~~~~~~~~
cbmbasic/runtime.c: In function ‘SAVE’:
cbmbasic/runtime.c:701:17: error: variable ‘savedbyte’ set but not used [-Wunused-but-set-variable]
  701 |   unsigned char savedbyte;
      |                 ^~~~~~~~~

cbmbasic/plugin.c: In function ‘plugin_gone’:
cbmbasic/plugin.c:242:18: error: variable ‘b’ set but not used [-Wunused-but-set-variable]
  242 |    unsigned char b;
      |                  ^

measure.c: In function ‘main’:
measure.c:225:6: error: this ‘if’ clause does not guard... [-Wmisleading-indentation]
  225 |      if (is_data_access)
      |      ^~
measure.c:228:7: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’
  228 |       if (IS_WRITE_CYCLE)
      |       ^~
measure.c:401:11: error: ‘end_p’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  401 |        if (end_p != readP(state)) {
      |           ^
measure.c:389:11: error: ‘end_s’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  389 |        if (end_s != readSP(state)) {
      |           ^

and also a link error:

cc -o cbmbasic/cbmbasic perfect6502.o netlist_sim.o cbmbasic/cbmbasic.o cbmbasic/runtime.o cbmbasic/runtime_init.o cbmbasic/plugin.o cbmbasic/console.o cbmbasic/emu.o measure.o
/usr/bin/ld: measure.o: in function `main':
measure.c:(.text.startup+0x0): multiple definition of `main'; cbmbasic/cbmbasic.o:cbmbasic.c:(.text.startup+0x0): first defined here
collect2: error: ld returned 1 exit status

Apply License to GitHub

Hello,

The comment text of the perfect6502.c file appears to grant usage of that file under the MIT license. However, the readme does not contain the license, and it is not tagged on GitHub as being under the MIT license, so it could be possibly construed that not all of the files are MIT. This is probably not your intent, so I was hoping you could apply the MIT license on GitHub as well as adding a comment to the readme.

Here is an example repo of mine that is MIT so you can see where it shows on GitHub. https://github.com/lukevp/ESC-POS-.NET

BRK sets I flag a half cycle earlier than in visual6502

The BRK instruction in perfect6502 sets the I flag a half cycle earlier than in visual6502. perfect6502 does it in phase 2 of the PCL-loading cycle, while visual6502 does it in phase 1 of the PCH-loading cycle (cycle 8, phase 1 in this simulation). The C code below shows what perfect6502 does.

I don't know if the difference in simulation is crucial; I certainly did not expect it, though.

TEST.c:

#include <stdio.h>
#include "types.h"
#include "perfect6502.h"
#include "netlist_sim.h"

int main(void)
{
    memory[0] = 0x58; /* CLI */
    memory[1] = 0x00; /* BRK */

    state_t *state = initAndResetChip();

    /* Cycle through the loading of the RESET vector. */
    for (int i = 0; i < 16; i++)
        step(state);

    printf("-- Fetching CLI:\n");
    for (int i = 0; i < 2; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing CLI:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing BRK (I flag cleared above [node p2=%d]):\n", isNodeHigh(state, 1421));
    for (int i = 0; i < 10; i++) {
        step(state);
        chipStatus(state);
    }

    printf("   perfect6502 sets I in phase 2 of PCL-loading cycle, -------------^^\n");
    printf("   but visual6502 sets I in phase 1 of PCH-loading cycle (below).\n");
    for (int i = 0; i < 2; i++) {
        step(state);
        chipStatus(state);
    }

    destroyChip(state);
    return 0;
}

$ gcc -Wall -o TEST TEST.c perfect6502.c netlist_sim.c

$ ./TEST output:

-- Fetching CLI:
halfcyc:17 phi0:0 AB:0000 D:00 RnW:1 PC:0000 A:00 X:C0 Y:00 SP:BD P:16 IR:00
halfcyc:18 phi0:1 AB:0000 D:58 RnW:1 PC:0000 A:00 X:C0 Y:00 SP:BD P:16 IR:00 R$0000=$58
-- Executing CLI:
halfcyc:19 phi0:0 AB:0001 D:58 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:16 IR:58
halfcyc:20 phi0:1 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:16 IR:58 R$0001=$00
halfcyc:21 phi0:0 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:12 IR:58
halfcyc:22 phi0:1 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:12 IR:58 R$0001=$00
-- Executing BRK (I flag cleared above [node p2=0]):
halfcyc:23 phi0:0 AB:0002 D:00 RnW:1 PC:0002 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:24 phi0:1 AB:0002 D:00 RnW:1 PC:0002 A:00 X:C0 Y:00 SP:BD P:12 IR:00 R$0002=$00
halfcyc:25 phi0:0 AB:01BD D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:26 phi0:1 AB:01BD D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BD=$00
halfcyc:27 phi0:0 AB:01BC D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:28 phi0:1 AB:01BC D:03 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BC=$03
halfcyc:29 phi0:0 AB:01BB D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:30 phi0:1 AB:01BB D:32 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BB=$32
halfcyc:31 phi0:0 AB:FFFE D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:12 IR:00
halfcyc:32 phi0:1 AB:FFFE D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00 R$FFFE=$00
   perfect6502 sets I in phase 2 of PCL-loading cycle, -------------^^
   but visual6502 sets I in phase 1 of PCH-loading cycle (below).
halfcyc:33 phi0:0 AB:FFFF D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00
halfcyc:34 phi0:1 AB:FFFF D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00 R$FFFF=$00

ANSI escape sequences

If you look at commit a66e209 in my fork you'll find ANSI escape sequences for Linux. They even work as far as I can tell writing BASIC programs. Sorry, it's not JUST the ANSI stuff in that commit, there are some unrelated changes as well. That's why I didn't send a pull-request yet. Let me know if you want me to do that.

Incorrectly emulated undocumented ANC instruction

As reported at forum6502:

This instruction is called stable, so I'd expect that visual6502 simulates it as described. However, it seems that A doesn't get updated at all (this seems to be incorrect, as ANC should behave almost like AND).

Here's the C code to reproduce the issue (slightly updated version of that posted in the above thread):

#include <stdio.h>
#include "types.h"
#include "perfect6502.h"
#include "netlist_sim.h"

#include <assert.h>

// gcc -Wall -o testANC testANC.c perfect6502.c netlist_sim.c


/*
 * $0B ANC #imm
 * $2B ANC #imm
 * 
 * ANDs the contents of the A register with an immediate value and then moves bit 7 of A
 * into the Carry flag.
 * 
 * See https://csdb.dk/release/?id=198357
 */

int main(void)
{
    memory[0] = 0xa9; /* LDA */
    memory[1] = 0xff; /* $ff */
    memory[2] = 0x38; /* SEC */
    memory[3] = 0x0b; /* ANC */ // 0x2b
    memory[4] = 0x00; /* $00 */
    memory[5] = 0xea; /* NOP */
    memory[6] = 0x00; /* BRK */

    state_t *state = initAndResetChip();

    /* Cycle through the loading of the RESET vector. */
    for (int i = 0; i < 16; i++)
        step(state);

    printf("-- Fetching LDA:\n");
    for (int i = 0; i < 2; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing LDA:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing SEC:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing ANC:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    unsigned char regA = readA(state);
    assert(regA == 0x00);

    unsigned char flags = readP(state);
    assert((flags & 0x01) == 0x00);

    printf("-- Executing NOP:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing BRK:\n");
    for (int i = 0; i < 10; i++) {
        step(state);
        chipStatus(state);
    }

    destroyChip(state);
    return 0;
}

perfect6502 not quite perfect...?

I've put a test program here: https://github.com/tom-seddon/perfect6502/tree/_brk

Repro steps:

get latest of https://github.com/tom-seddon/perfect6502/tree/_brk
make
./cbmbasic

This clears memory, sets IRQ vector to 0x30, reset vector to 0x10, and runs the 6502 for 50 half cycles.

Expected result:

6502 hits the BRK, does its usual thing, and starts executing from 0x0030

Actual result:

6502 hits the BRK, does its usual thing, and starts executing from $4777

Notes:

This is intended to be the same as the following visual6502 link: http://visual6502.org/JSSim/expert.html?a=0000&d=000000000000000000000000000000000000000000000000&a=0030&d=ea&a=fffc&d=100030&graphics=false&steps=50 (and visual6502 behaves as I'd expect in this case)

Thanks,

--Tom

Unclear start conditions due to memory pollution

The simulation starts in unclear conditions as setupNodesAndTransistors function does not clear the memory it allocates, leading to odd results at times. This is not a problem for the MOS 6502 netlist as it does the RESET. But it can be suprising if netlist_sim is used independently.