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Python script for controlling the debug-jtag port of riscv cores

Python 22.46% Verilog 45.42% C++ 2.68% Makefile 1.63% Shell 0.61% SystemVerilog 16.95% Tcl 0.32% Stata 0.06% Assembly 5.87% C 2.88% Dockerfile 0.01% HTML 0.09% CSS 0.01% Perl 0.03% TeX 0.72% CMake 0.02% M4 0.01% JavaScript 0.02% Scala 0.15% SCSS 0.06%

riscv32 python jtag ocd verilog

pyocdriscv32's Introduction

PyOCD-RISCV32

Generating with a pythonscript JTAG-sequences for the debug port of different RISCV32 cores:

using the API of pyftdi.

To try it in simulation verilator is needed. For pulp do the following: Build the firmware pulp.bin: python3 mkfw.py pulp floathw rvf

Build the simulation: cd pulp make all Run the simulation: output_verilator/riscv_soc or with tracing enabled: output_verilator/riscv_soc vcd Finally run dbgjtag.py: python3 dbgjtag.py s pulp

To use it on real hardware (with an ARM-USB-TINY-H): python3 dbgjtag.py f pulp

with an USB-Blaster and virtual JTAG: python3 dbgjtag.py v murax

pyocdriscv32's People

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mfkiwl chipyard riscvnexus

pyocdriscv32's Issues

VJTAG with Altera board

Hi,
I'm trying to use vjtag with DE10Lite board. My expectation is with single USB connection, we can both programming the board as well as debuging the app run on murax core.
is that possible with this project https://github.com/michg/pyocdriscv32/tree/master/murax/quartus/virtual?
I had tried it but I'm not sure this vjtag support this

10M50.tap
Info : set servers polling period to 50ms
Info : No lowlevel driver configured, using ftdi
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: 10M50.tap tap/device found: 0x031050dd (mfg: 0x06e (Altera), part: 0x3105, ver: 0x0)
Info : starting gdb server for saxon.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Halting processor
requesting target halt and executing a soft reset
 done
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'gdb' connection on tcp/3333
Info : New GDB Connection: 1, Target saxon.cpu0, state: halted
Warn : Prefer GDB command "target extended-remote :3333" instead of "target remote :3333"
Info : Halt timed out, wake up GDB.
Warn : target saxon.cpu0 is not halted (gdb fileio)
openocd: src/target/vexriscv.c:1233: vexriscv_read_memory: Assertion `target->state == TARGET_HALTED' failed.
Aborted (core dumped)

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