mazince / veecom Goto Github PK

notice that

make && make bin

under project template folder and then load the bin file into logicsim-evolution v3.8.0 memory do not print hello world as excepted, project template/main.c lack one line of code which is

WRITE_BYTE(DDRA, OUTPUT);

Thank you very much for your data and all information !!!!
But it would be complicated because lack of knowledge....
"Load the generated binary file into the first bank in the memory module." Would you pls give me which bin files should be loaded ?
my folder "C:\SysGCC\risc-v\bin" has many kinds of files? But I would not know which one?
pls help me ?

Beow ones , how to do it? I am sorry that I would have lack of knowledge for " RISC-V C/C++ compiler" . Please give me some more detailed information ? For demo, I followed your instrcuction, I could do it, but below ones I don't have any idea what I do.
Thank for your data and other information which I could understand RISC V a little more.
"You'll need a RISC-V C/C++ compiler, I personaly use this one for my windows machine https://gnutoolchains.com/risc-v/
Load the generated binary file into the first bank in the memory module.
Tested in Logisim-evolution v3.7.2"