The goal of this project is to ease elastic overlay generation. It is somehow a back-end for the whole elastic overlay project. This project was initialized using the Chisel Project Template found on Chisel3 project. All you can find the overlay package in src directory. Some modules have Scala test benches. It is a work in progress.

If you haven't worked with Chisel before, head to this tutorial.

Every module has an object for Verilog generation. To generate Verilog simply do the following from project's parent directory:

sbt 'runMain overlay.$MODULE_NAME $ARGS'

where $MODULE_NAME is name of the module and $ARGS is arguments to pass to Chisel Driver. You can see a list of option by passing --help as the $ARGS list.

if the module has Scala test associated with it you can run the test using

sbt `testOnly overlay.${Module_Name}Spec`

##Out of Memory Exception Overlay generation usually requires more than 1GBs of memory which is the default memory size for the underlaying JVM in sbt. Therefore it is better to start sbt with more memory. To do this, run:

export SBT_OPTS="-Xmx4G"
sbt

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