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hx8k-sram16-extension's Issues

Optimize pin use for FPGA banks?

Hi,

This is a really cool design! I am planning to use a portiona of it (the SRAM bits) and I was wondering if you had thought at all about how the IO use maps to the FPGA IO banks? I was considering have all address + control lines on one bank with the data lines on another to help the place+route optimize a bit better. Does that make any sense?

[Question] Dimensions

Hi, thanks for this and your other repository that offer these neat extension boards.
I wanted to roll my own HX8K breakout board extension and figured out the dimensions on the board a wildly mixed (inch and mm, plus sometimes there is no obvious reference by which some parts are placed there).
When I checked both your board designs I see that once the pin header are apart by 9.2128 mm and once by 9 mm for the same measurement.
I currently can't accurately measure my ICE40HX8K-B-EVN board, but my estimate says 9.2128 is more correct, as 9 mm would be too little for that measurement.

I'm glad about your repos tho, it's the only available board for that breakout board I found so far that provide some useful references.

I wanted to roll a board with all 4 headers on an extension board if possible, but from the breakout board itself I cant really figure out proper dimensions so far. Pretty undocumented, which is why your repos are an oasis in that regard 💯

I thought to maybe bounce a few ideas here while asking that if you dont mind.

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