You can find the paper here. You can find the conference presentation video here.

docker build -t evalimage .

docker run -it -v "$(pwd)":/mnt evalimage /bin/bash

sh /mnt/post-script.sh

The architectural generator enables custom creation of the architecture described in the paper for any arbitrary task parallel algorithm described in Cilk syntax.

1. Specify the JSON descriptor file for the code you to generate its circuit. An example descriptor for the fib example in the paper can be found in this link.
2. In the architecture-generator directory run:

   exec sbt "runMain fullSysGen.CommandLineEmitter <path_to_JSON_file>"

3. You can find the output Verilog files in the output directory under the architecture-generator directory. The output Verilog has AXI4 and AXI-stream interfaces that you can easily integrate with your PEs and memory system. The interfaces are also compliant with the Vivado IP integrator which makes it easier to connect the ports.

cd ~/repos/HardCilk/architecture-generator/ && exec sbt "runMain fullSysGen.ServerEmitter"

docker ps

docker exec -it <container-id> /bin/bash

python3 run_evaluation.py