lucysrausch / colorlight-led-cube Goto Github PK

7.35.37.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 1
ABC RESULTS: ANDNOT cells: 1
ABC RESULTS: BUF cells: 304
ABC RESULTS: DFF cells: 160
ABC RESULTS: NAND cells: 2
ABC RESULTS: NOT cells: 17
ABC RESULTS: XNOR cells: 1
ABC RESULTS: XOR cells: 2
ABC RESULTS: internal signals: 22
ABC RESULTS: input signals: 164
ABC RESULTS: output signals: 165
Removing temp directory.

7.36. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
ERROR: Conflicting init values for signal 1'1 (\eternit.ip_tx_liteethipv4checksum_r_next0 [2] = 1'x != 1'0).
Makefile:19: recipe for target 'top.json' failed
make: *** [top.json] Error 1

7.39. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
ERROR: Conflicting init values for signal 1'0 (\eternit.ip_tx_liteethipv4checksum_r_next0 [1] = 1'0 != 1'x).
make: *** [Makefile:19: top.json] Error 1

this is running make top.svf in the fpga/syn folder.

I noted that to use this I had to flash new firmware; wondering then if it's possible to edit that firmware to include full color support instead of gamma correction.

Hi,
i am able to build & send the top.svf and it works fine, but when i try to flash the flash.svf i get the following error :
Error: tdo check error at line 36 Error: READ = 0x0601f10 Error: WANT = 0x0000000 Error: MASK = 0x000b000 Error: fail to run command at line 3025 Error: tdo check error at line 36 Error: READ = 0x0601f10 Error: WANT = 0x0000000 Error: MASK = 0x000b000

The firmware out of the box would have supported this. It is only partly documented but there are projects which use the L2 Ethernet protocol. See mine for reference.

ColorLight allows netcard, which is using PC as sender card. This was very smart on their part. It would be interesting to know the protocol used by others, but that would require a sender card purchase. However ColorLight does not. This may have been intended as a test feature however it is a nice feature for adding custom logic outside of sender card functionality.

You can close this out, since this the only way for me to really post this without the discussions feature enabled.

This is an awesome project, but could you please give some hints on how to change the resolution?
I only have 32x64 pixel panels and I am a total n00b with Verilog, because I have never used it before.
Thanks a lot for this project :D

I cant't seem to compile with V8.0 pinout. I have changed the top.lpf to match version 8.0 pins.

Info: Packing IOs..
Info: pin 'CLK$tr_io' constrained to Bel 'X0/Y32/PIOD'.
Info: pin 'B$tr_io' constrained to Bel 'X0/Y35/PIOD'.
Info: pin 'A$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led$tr_io' constrained to Bel 'X4/Y50/PIOA'.
Info: pin 'osc25m$tr_io' constrained to Bel 'X0/Y47/PIOC'.
Info: pin 'rgmii_rx_clk$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: pin 'rgmii_rxd[0]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'rgmii_rxd[1]$tr_io' constrained to Bel 'X0/Y20/PIOC'.
Info: pin 'rgmii_rxd[2]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: pin 'rgmii_rxd[3]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'rgmii_rx_ctl$tr_io' constrained to Bel 'X0/Y23/PIOB'.
Info: pin 'rgmii_tx_clk$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'rgmii_txd[0]$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'rgmii_txd[1]$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'rgmii_txd[2]$tr_io' constrained to Bel 'X0/Y35/PIOA'.
Info: pin 'rgmii_txd[3]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'rgmii_tx_ctl$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'mdio_scl$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: pin 'mdio_sda$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'button$tr_io' constrained to Bel 'X6/Y50/PIOA'.
Info: pin 'phy_resetn$tr_io' constrained to Bel 'X4/Y50/PIOB'.
Info: pin 'R0[1]$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'G0[1]$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'B0[1]$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'R1[1]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'G1[1]$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'B1[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'C$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: pin 'D$tr_io' constrained to Bel 'X0/Y41/PIOA'.
Info: pin 'E$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'LAT$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: pin 'OE$tr_io' constrained to Bel 'X0/Y35/PIOC'.
Info: IOLOGIC component eternit.DELAYG connected to PIO Bel X0/Y26/PIOA
terminate called after throwing an instance of 'nextpnr_ecp5::assertion_failure'
what(): Assertion failure: is_string (/home/travis/build/xobs/toolchain-nextpnr-ecp5/_builds/build_linux_x86_64/nextpnr/common/nextpnr.h:340)
make: *** [Makefile:22: top.config] Aborted (core dumped)

After changing the IP addr at liteeth.yml and
make ../liteeth_core.v

when I make top.svf again, i get the error below

Info: Packing IOs..
Info: pin 'CLK$tr_io' constrained to Bel 'X72/Y2/PIOA'.
Info: pin 'B$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: pin 'A$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'led$tr_io' constrained to Bel 'X72/Y47/PIOC'.
Info: pin 'osc25m$tr_io' constrained to Bel 'X0/Y47/PIOC'.
Info: pin 'rgmii_rx_clk$tr_io' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'rgmii_rxd[0]$tr_io' constrained to Bel 'X0/Y32/PIOA'.
Info: pin 'rgmii_rxd[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'rgmii_rxd[2]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'rgmii_rxd[3]$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'rgmii_rx_ctl$tr_io' constrained to Bel 'X0/Y47/PIOB'.
Info: pin 'rgmii_tx_clk$tr_io' constrained to Bel 'X0/Y26/PIOD'.
Info: pin 'rgmii_txd[0]$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'rgmii_txd[1]$tr_io' constrained to Bel 'X0/Y32/PIOC'.
Info: pin 'rgmii_txd[2]$tr_io' constrained to Bel 'X0/Y32/PIOB'.
Info: pin 'rgmii_txd[3]$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: pin 'rgmii_tx_ctl$tr_io' constrained to Bel 'X0/Y32/PIOD'.
Info: pin 'mdio_scl$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: pin 'mdio_sda$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: pin 'button$tr_io' constrained to Bel 'X72/Y35/PIOC'.
Info: pin 'phy_resetn$tr_io' constrained to Bel 'X0/Y47/PIOD'.
Info: pin 'R0[0]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'R0[1]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'R0[2]$tr_io' constrained to Bel 'X72/Y47/PIOA'.
Info: pin 'R0[3]$tr_io' constrained to Bel 'X72/Y23/PIOC'.
Info: pin 'R0[4]$tr_io' constrained to Bel 'X72/Y17/PIOB'.
Info: pin 'R0[5]$tr_io' constrained to Bel 'X67/Y0/PIOB'.
Info: pin 'G0[0]$tr_io' constrained to Bel 'X0/Y29/PIOB'.
Info: pin 'G0[1]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'G0[2]$tr_io' constrained to Bel 'X72/Y47/PIOB'.
Info: pin 'G0[3]$tr_io' constrained to Bel 'X72/Y23/PIOB'.
Info: pin 'G0[4]$tr_io' constrained to Bel 'X72/Y17/PIOC'.
Info: pin 'G0[5]$tr_io' constrained to Bel 'X72/Y14/PIOA'.
Info: pin 'B0[0]$tr_io' constrained to Bel 'X0/Y35/PIOA'.
Info: pin 'B0[1]$tr_io' constrained to Bel 'X0/Y20/PIOA'.
Info: pin 'B0[2]$tr_io' constrained to Bel 'X72/Y47/PIOD'.
Info: pin 'B0[3]$tr_io' constrained to Bel 'X72/Y23/PIOA'.
Info: pin 'B0[4]$tr_io' constrained to Bel 'X72/Y17/PIOA'.
Info: pin 'B0[5]$tr_io' constrained to Bel 'X65/Y0/PIOB'.
Info: pin 'R1[0]$tr_io' constrained to Bel 'X0/Y35/PIOB'.
Info: pin 'R1[1]$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'R1[2]$tr_io' constrained to Bel 'X72/Y23/PIOD'.
Info: pin 'R1[3]$tr_io' constrained to Bel 'X72/Y17/PIOD'.
Info: pin 'R1[4]$tr_io' constrained to Bel 'X72/Y14/PIOC'.
Info: pin 'R1[5]$tr_io' constrained to Bel 'X62/Y0/PIOB'.
Info: pin 'G1[0]$tr_io' constrained to Bel 'X0/Y29/PIOD'.
Info: pin 'G1[1]$tr_io' constrained to Bel 'X0/Y5/PIOB'.
Info: pin 'G1[2]$tr_io' constrained to Bel 'X72/Y44/PIOD'.
Info: pin 'G1[3]$tr_io' constrained to Bel 'X72/Y20/PIOB'.
Info: pin 'G1[4]$tr_io' constrained to Bel 'X72/Y14/PIOD'.
Info: pin 'G1[5]$tr_io' constrained to Bel 'X67/Y0/PIOA'.
Info: pin 'B1[0]$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'B1[1]$tr_io' constrained to Bel 'X0/Y5/PIOC'.
Info: pin 'B1[2]$tr_io' constrained to Bel 'X72/Y26/PIOA'.
Info: pin 'B1[3]$tr_io' constrained to Bel 'X72/Y20/PIOA'.
Info: pin 'B1[4]$tr_io' constrained to Bel 'X72/Y14/PIOB'.
Info: pin 'B1[5]$tr_io' constrained to Bel 'X65/Y0/PIOA'.
Info: pin 'C$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'D$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'E$tr_io' constrained to Bel 'X72/Y11/PIOC'.
Info: pin 'LAT$tr_io' constrained to Bel 'X72/Y20/PIOC'.
Info: pin 'OE$tr_io' constrained to Bel 'X72/Y8/PIOD'.
Info: IOLOGIC component eternit.DELAYG connected to PIO Bel X0/Y26/PIOD
terminate called after throwing an instance of 'nextpnr_ecp5::assertion_failure'
what(): Assertion failure: is_string (/home/travis/build/xobs/toolchain-nextpnr-ecp5/_builds/build_linux_x86_64/nextpnr/common/nextpnr.h:340)
make: *** [Makefile:22: top.config] Aborted (core dumped)