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lora_gateway's Introduction

 / _____)             _              | |    
( (____  _____ ____ _| |_ _____  ____| |__  
 \____ \| ___ |    (_   _) ___ |/ ___)  _ \ 
 _____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
  (C)2013 Semtech-Cycleo

LoRa Gateway project

  1. Core library: libloragw

This directory contains the sources of the library to build a gateway based on a Semtech LoRa multi-channel RF receiver (a.k.a. concentrator). Once compiled all the code is contained in the libloragw.a file that will be statically linked (ie. integrated in the final executable).

The library also comes with a bunch of basic tests programs that are used to test the different sub-modules of the library.

  1. Helper programs

Those programs are included in the project to provide examples on how to use the HAL library, and to help the system builder test different parts of it.

2.1. util_pkt_logger

This software is used to set up a LoRa concentrator using a JSON configuration file and then record all the packets received in a log file, indefinitely, until the user stops the application.

2.2. util_spi_stress

This software is used to check the reliability of the link between the host platform (on which the program is run) and the LoRa concentrator register file that is the interface through which all interaction with the LoRa concentrator happens.

2.3. util_tx_test

This software is used to send test packets with a LoRa concentrator. The packets contain little information, on no protocol (ie. MAC address) information but can be used to assess the functionality of a gateway downlink using other gateways as receivers.

2.4. util_tx_continuous

This software is used to set LoRa concentrator in Tx continuous mode, for spectral measurement.

2.5. util_spectral_scan

This software is used to scan the spectral band in background, where the LoRa gateway operates.

2.6. util_lbt_test

This software is used to test "Listen-Before-Talk" channels timestamps.

  1. Helper scripts

3.1. reset_lgw.sh

This script must be launched on IoT Start Kit platform to reset concentrator chip through GPIO, before starting any application using the concentrator.

  1. Changelog

v5.0.1

  • HAL: Reworked the way the TX start delay is calculated, taking into account the delay introduced by TX notch filter (when enabled) and the delay linked to signal bandwidth separately.

v5.0.0

  • HAL: Changed GPS module to get native GPS time (monotonic, no leap second). WARNING: The native GPS time is not given in standard NMEA messages, so we get it from a proprietary message of the GPS module used on gateway reference design, u-blox 7. If you are not using the same GPS module, you may have to update the lgw_parse_ubx() function.
  • HAL: Added lgw_cnt2gps() and lgw_gps2cnt() functions for SX1301<->GPS time conversion.
  • HAL: Changed serial port configuration for GPS to properly handle binary messages (UBX).
  • HAL: Added a lgw_gps_disable() function to restore serial configuration as it was before HAL initialization.
  • HAL: Fixed packet time on air calculation using the actual packet preamble size.
  • HAL: Adjusted TX_START_DELAY based on the board reference design to ensure that a packet is sent exactly at 1500µs after the TX trigger (TIMESTAMP or PPS), with a tolerance of +/- 1µs. This is mandatory to comply with LoRaWAN specification for Class-B beaconing precise timing. WARNING: This release provides tx start delay values to be used for Semtech reference designs AP1 and AP2. The HAL automatically detects the board version by detecting a FPGA or not. If you are using a different reference design or a different FPGA binary version than the one provided with this release, the value to be used for TX start delay may be different.

v4.1.3

  • HAL: Reference clock frequency error improvement: The lora_gateway HAL has been updated (3 registers changed) to improve the performance of all gateways based on SX130x. The fix greatly improves the reception of packet at SF12, when the frequency offset of the incoming packet is large (mostly below -20ppm of frequency offset).

WARNING: Systems which do not have the patch will be more prone to packet loss over time, when the crystals of the end-devices will be ageing and have more frequency offset.

v4.1.2

  • HAL: Changed configuration of IQ polarity of FPGA for TX to comply with FPGA version greater than v27. (Only required for AP2 Semtech reference design)
  • HAL: Updated default LoRa preamble size according to LoRaWAN spec.

v4.1.1

  • HAL: Fixed bug in "Listen-Before-Talk" which was preventing from configuring the Scan Time to 5ms.
  • MISC: Added GPIO number to reset_lgw.sh command arguments.

v4.1.0

  • HAL: Reworked "Listen-Before-Talk" feature to have more flexibility to define LBT channels frequency, and to be able to have spectral scan running in parallel
  • HAL: Updated lgw_time_on_air() function for FSK packets
  • HAL: Disabled GPS UART input being re-echoed as output to avoid sending wrong commands to GPS module
  • HAL: Fixed IF frequency configuration check issue for channel bandwidths 250K and 500HKz.
  • FPGA: Updated to v31 for new LBT and spectral scan design.
  • util_spectral_scan: updated to match new spectral scan FPGA sequence
  • util_lbt_test: updated to match LBT rework

Note: The provided LBT feature has been validated for Japan only, and supports 8 downlink channels maximum.

v4.0.1

  • HAL: SX1301AP2: Only FPGA v27 is supported, removed (v18,v19) from the list of supported FPGA images.

WARNING: If you are using a Semtech SX1301AP2 ref design (GW1.5), the FPGA must be reprogrammed with one of the images provided with this release (fpga/ dir).

v4.0.0

  • HAL: Added "Listen-Before-Talk" support for Semtech SX1301AP2 Ref Design. A description of the feature implementation can be found in libloragw/readme.md.
  • HAL: Updated FSK RSSI calculation for better linearization
  • util_lbt_test: New utility provided for basic "Listen-Before-Talk" testing.
  • util_tx_test: Extended to configure and test "LBT" through the HAL.
  • Added a reset_lgw.sh script to be used with IoT Starter Kit (v1.0) to reset the concentrator through the HOST GPIO pin.

v3.2.1

  • HAL: Fixed downlink support for SX1301AP2 reference design: soft reset of the FPGA was missing for proper IQ inversion configuration.
  • HAL: Added support for several versions of FPGA (currently v18 and v19)
  • HAL: Reduced radio TX PLL bandwidth to reduce the noise level.
  • util_tx_test: Added FSK support and added minimal TX gain LUT.
  • util_spectral_scan: Removed FPGA soft reset, now done by the HAL.
  • util_tx_continous: reworked to use HAL functions instead of 'manual' config, and use same SX1301 calibration firmware as the HAL.
  • Updated all makefiles to handle the creation of obj directory when necessary.
  • Change cs_change usage policy in SPI module to let the driver handle the chip select.

v3.2.0

  • Added support for SX1301AP2 reference design (with FPGA and additional SX127x). When a FPGA is detected at startup, the HAL automatically adapts SPI communication requests (using SPI header or not).
  • Added util_spectral_scan diagnostic tool to scan the spectral band in background, where the LoRa gateway operates. (can only be used with SX1301AP2 or similar design). By default it uses the same SPI device as the one used by the HAL, but it can be changed depending on the hardware architecture on which it is used by updating the SPI_DEV_PATH constant defined in file util_spectral_scan/src/loragw_fpga_spi.c. Note: when using same SPI device from 2 applications, we rely on the host SPI driver and OS to properly handle concurrent SPI requests. It has been tested on Raspberry Pi / Raspbian with spi_bcm2708 driver.* Removed SPI FTDI support due to lack of performances to properly handle heavy packet traffic. Only native SPI usage is recommended.
  • HAL: added a check that SX1301 firmwares have been properly loaded at startup.

v3.1.0

  • Removed GPIO module from HAL, that was specific to IoT Starter Kit platform. GPIO configuration will be done from application script instead.
  • Removed CFG_BRD configuration from library.cfg, not needed anymore

v3.0.2

  • Bugfix: Fixed frequency calculation on uplinks: lgw_receive() function was using a variable to calculate the frequency before it was initialized with correct value.
  • Bugfix: util_pkt_logger crashed when no gateway_ID is not defined in global_conf.json

v3.0.1

  • Bufgix: Fixed util_tx_continuous compilation issue, by adding empty obj directory
  • Bugfix: Fixed HAL compilation issue for CFG_SPI=ftdi, removed dependency on loragw_gpio in this case

v3.0.0

  • Added new HAL function lgw_board_setconf() to configure board/concentrator specific parameters: network type (LoRa public or private), concentrator clock source. Note: those parameters are not any more set from the library.cfg file configuration (CFG_NET, CFG_BRD), and should be passed at initialization by the application.
  • Added new HAL function lgw_txgain_setconf() to configure concentrator TX gain table. It can now be dynamically set by the application at initialization time.
  • Changed HAL function lgw_rxrf_setconf(), it will now also configure the radio type (CFG_RADIO has been removed from library.cfg), the RSSI offset to be used for this radio and if TX is enabled or not on this radio.
  • Added support of IoT Starter Kit platform, which is now the default board.
  • Added util_tx_continuous utility for gateway TX power calibration and spectral emission measurements/qualification.
  • Removed CFG_BAND configuration from library.cfg. Band configuration is done by application and passed dynamically at initialization time.
  • Updated makefiles to allow cross compilation from environment variable (ARCH, CROSS_COMPILE).

** WARNING: ** ** Known issue: a problem with carrier leakage calibration has been seen on 433MHz boards. **

v2.0.0

  • Added support for Kerlink 868 27dBm gateway
  • Updated global_conf.eu868.json (in packet logger) to new LoRaWAN frequency plan
  • Added version numbers to AGC, arbiter and calibration firmware (those versions are checked at startup)
  • Added test_loragw_cal to test radio calibrations
  • Fixed minor bug in error coverage in register read/write functions

/!\ warning: Kerlink 868 27dBm gateway includes a FPGA that MUST be programmed before running any application

v1.7.0

  • Added TX 'start delay' compensation for timestamp mode (fix time window alignment issue at low SF and/or high BW)
  • Added adaptive narrowband/wideband TX filtering for LoRa
  • Added a command-line option to set CR in util_tx_test
  • Added notes for TX 'start delay' in immediate and triggered mode

/!\ warning: due to start delay compensation being implemented, TX that were previously 1.5ms late will be sent on time. At low datarate, this is not an issue. At high LoRa data rate (and FSK) you might have to adjust your timing.

v1.6.0

  • Fixed bug with 250kHz and 500 kHz TX filtering
  • Adjusted FSK timestamp calibration in RX for accurate RX/TX alignment
  • Added lgw_abort_tx() function to stop a TX at any time (scheduled or ongoing)
  • Added support for user-settable FSK sync word (same for RX and TX)
  • Added support for the Chinese 780 MHz band
  • Added support for Kerlink 433 gateway
  • Added support for Cisco 433, 470 & 780 MHz concentrators boards

v1.5.0

  • Adding option to isolate public LoRa MAC networks at PHY level.

v1.4.1

  • Enabling support for FSK per LoRa MAC specification
  • Adjusting TX and RX calibration set on 868 reference board
  • Added specific RX/TX calibration set for Kerlink 868 "IoT station" gateway
  • Changed default SPI port for native driver to Kerlink SPI device number

v1.4.0

  • Added calibration routine to optimize RF performance
  • Added support for SX1301 433 MHz reference board
  • Improved AGC firmware
  • Improved RSSI accuracy
  • Improved utilities Makefile

v1.3.0

  • Added TX power management.
  • Added full support for SX1301 reference board.
  • Changed build system with configuration for multiple chip/radio/band support.
  • SX125x bandwidth set to 1MHz by default (was 800 kHz).
  • Solved warnings with 64b integer printf when compiling on x86_64.
  • Renamed helper programs to reduce the concentrator vs. gateway confusion.

v1.2.2

  • Added a GPIO toggle on the FTDI SPI module to reset the SX1301 board.

v1.2.1

  • Fixed 'floating point exception' crash when concentrator returned a packet with SF=0 (CRC error on LoRa header).
  • Fixed buggy timezone handling.

v1.2.0

  • Added feature: new GPS module in the library for synchronization.
  • Removed feature: no more missed deadline detection in TX because of incompatibility with GPS.
  • Added documentation for GPS and legal notice.
  • Added flags in Makefiles for easier cross-compilation.

v1.1.0

  • Fixed bug 'no TX on radio B' (rfch 1).
  • Added feature: concentrator processing delay compensation in the receive() function for accurate 'end of packet' even timestamping.
  • Added feature: TX 'start delay' compensation in the send() function to emit packet exactly on target timestamp.
  • Added feature: timestamp counter verification in send() function, return an error if scheduling was too late.
  • Switched license to 'Revised BSD'.

v1.0.0 (from beta 8)

  • Switched FTDI as default SPI phy layer in library.cfg.
  • Fixed a bug in TX power control; still only two TW power available, 14 and 24dBm.
  • Changed library directory name from loragw_hal to libloragw to follow usual conventions.

Beta 8 (from beta 7)

  • API: lgw_receive now return info on RX frequency and RF path for each packet (no need to keep track of RF/IF settings).
  • Unified some portion of the code with the 470 MHz variant of the HAL (use SX1255 radios instead of SX1257).
  • Improved AGC and ARB firmwares.
  • Adding -Wall -Wextra for compilation, fixing all the new warnings for cleaner code.
  • Fixed bugs in handling of FSK datarate.
  • test_loragw_hal now dumps the content of all LoRa registers after configuration in reg_dump.log.

Beta 7 (from beta 5)

  • Reduced number of SPI transactions to fetch a packet (improved number a packets par second that can be downloaded from concentrator).
  • Streamlined build process, main target is now a static library: libloragw.a.
  • Change memory allocation for payload: they are now part of the struct for TX/RX, no need to malloc/free.
  • All RX chains can use any of the two radios now.
  • FSK is available and working in TX and RX (variable length mode).
  • Calibrated RSSI for FSK.
  • lgw_connect now check the CHIP_ID.
  • Added a license file and a changelog.
  • Added a function returning a version string to allow identification of the version/options once compiled.

Beta 6

Private release, not taken into account in that changelog.

Beta 5 (from beta 4)

  • Updated registers, firmware and configuration to align with r986 bitstream revision.
  • Calibrated RSSI for LoRa "multi" and LoRa "stand alone" modems.
  • Renamed some confusing TX status code.
  • Added preliminary FSK support.

Beta 4 (from beta 3)

  • Unified build environment with selectable SPI layer (Linux native or FTDI SPI-over-USB bridge).
  • Remove the 500 kHz limit on radio bandwith, back to the nominal 800 kHz.
  • Renamed debug flags.
  1. Legal notice

The information presented in this project documentation does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range.

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

EOF

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lora_gateway's Issues

check duplicated packets

I came across the as problem in the issue below:
brocaar/chirpstack-network-server#159
The node sent first packet to gateway, gateway received packet but didn't response to it.
So the node sent same data again but used a different frequency and expected a different receive frequency.And the server handled first packet, drop the latter one.
Although gateway received first packet response, data couldn't be transferred to node.
I wonder is it better to check duplication on gateway or on server?

Downlink ACK problem when two or more node working

Hi, I have a problem ,
when I use one node to test downlink ACK PER, everything works fine(PER about 1.5%), But when I use two or more nodes to test ,I found some problem(PER about 20-30%), Here is step

  1. node 1 send a confirm data.
  2. server respond a ACK to node 1 by gateway.
  3. Gateway send the ACK to node 1 at time_0.
  4. Node 2 send a uplink to gateway at time_1.
  5. If time_1 - time_0 < 500ms, the problem comes, node 1 can not receive ACK.
    I check gateway log , it shows that gateway has sent the ACK successful , and power meter shows GW has sent the ACK
    How can I solve this problem ? thx
    Best regards.

SX1301 reference board with version 1.2.x of library

When using version 1.2.x of the library, the SX1301 is not fully supported:

  • sensitivity is bad (eg. -127dBm for SF12/125kHz, instead of -141dBm) due to gain settings being optimized only for the FPGA-based board
  • the multi-SF RX channels 4 to 7 are not usable
  • the RSSI value is not properly calibrated and has an offset of 11 dBm

Support for SX1301 boards is scheduled for version 1.3 and beyond.

No TX on RF channel 1 (radio B)

Impossible to use RF channel 1 (radio B) to send packets, the TX won't work.

Concentrator return OK status, but nothing is emitted.
Bug due to clock signals.

the question about setup_sx125x

Hi,We have designed a lora gateway board base SX1301 and SX1255.We have run the Test_loragw_spi and Test loragw_reg program,and get the right result.But,the Test_loragw_hal_c program cann't get the right result.
We analy the process,and find

  1. the SX1301 cannot communicate with the SX1255 by the SPI_A or SPI_B,the NSS pin of SPI_A and SPI_B is always in high-level,and the SCK pin of SPI_A or SPI_B have no singal.
    2)we test the SX1255 by using the STM32F103 cpu,we can get every register's value.
    so,we want to know how to realize the communication between SX1301 and SX1255.

Changing KHZ, bandwidth of a channel

Good day,

Is it possible to change channel settings as following?

"chan_multiSF_0": {
/* Lora MAC channel, 125kHz, all SF, 868.1 MHz */
"enable": true,
"radio": 1,
"if": -400000,
"bandwidth": 7800,
"datarate": 585
}

I want channel to operate on 7.8kHz and width 585bps

LoRaWAN Gateway Settings

Hi,

I am working on microchip LoRa RN 2483 -raspberry pi c 2011 gateway and I have to set server ip and ports. But on the instructions of semtech network server gateway settings, there are files such as sys_config or global_config but I do not have them on raspberry so I download packet forwarder to get that files. But on the cooking-hacks site where I have instructions for raspberry site, they do not have such instructions and no mention about packet forwarder nor lora gateway application. Do you have any suggestion? Should I go on witht this code and packet forwarder or is it different?
I have arduPi lib and LoRaWAN lib so far.

*on the cooking hacks site they suggested to follow semtech's instructions but I need your confirmation if this app and packet forwarder suitable also my network devices.
Thanks in advance...

util_pkt_logger fail

Hi,
I tried running the util_pkt_logger with a SX1272 Lora emmitter but the messages aren't written in the log file.
This is what is in the csv file:
gateway ID,"node MAC","UTC timestamp","us count","frequency","RF chain","RX chain","status","size","modulation","bandwidth","datarate","coderate","RSSI","SNR","payload"
AA555A0000000101,"","2016-07-26 15:16:44.638Z", 68840907, 867600000,1, 0,"CRC_BAD",193,"LORA",125000,"SF7" ,"4/5",-120,-11.2,"96EE29AF-EDBCB2D4-4F920837-B95474B7-7485BE39-450C3D33-0193FAD0-6FC5A145-B0E50CF4-47394762-A6CB57FD-791D2B4A-ADE6291B-6F48C89A-C89D5275-5056CFC0-3421BBFE-32F61CE1-626CE2DC-6CC7AA3D-694E7300-1D1392CC-DE9D9A3C-B815B48B-33E94415-B4C3EE44-00A88D8A-C6F9FAB5-B274662F-495E6761-BFCEBE0C-BEB0294B-27953B9A-4D3B6F8A-D383AB35-69FE0B05-D696BAEC-7EC45408-76BC0CEA-8BD07ED7-A9F2F137-5EAD1E20-403A824C-60DFBBF0-0A030D7E-D3F3165C-AEFFCAE4-B8E67211-8A"

Can anyone help?
Am I reading the csv file wrong?

Hi,FPGA for CN470.hex

Hi, Is there a SX1301_FPGA_200K_NOTCH_LBT_SPECTRAL_SCAN_863_v33.hex corresponding to the CN470 file?

Internals of "delayed" packet forwarding

Hi,
Could anybody point to the internals of "delayed" packet forwarding ?

I could see the timestamp handling at Packet Forwarder and passed as metadata to lora_gateway through lgw_send().
The timestamp is put at buff (libloragw/src/loragw_hal.c)
1481 if (pkt_data.tx_mode == TIMESTAMPED)
1482 {
1483 count_trig = pkt_data.count_us - TX_START_DELAY;
1484 buff[3] = 0xFF & (count_trig >> 24);
1485 buff[4] = 0xFF & (count_trig >> 16);
1486 buff[5] = 0xFF & (count_trig >> 8);
1487 buff[6] = 0xFF & count_trig;
1488 }
Appreciate if any body could tell me how writing to LGW_TX_TRIG_DELAYED works 👍
lgw_reg_w(LGW_TX_TRIG_DELAYED, 1);
Is the send maintaining multiple buffers in the queue based on timestamp to send ?

Thanks

Preamble length hardcoded in lgw_time_on_air()

The lgw_time_on_air() function currently hard codes the preamble length to 8 symbols for it's calculation of the TOA. It should use the preamble length of the packet that is passed in via: packet->preamble.

Running iC880a-SPI with RS Pi3

I tried reseting my gateway iC880a-SPI using command $ sudo ./reset_lgw.sh start and left the code running for 1 minute.

how does the actual process starts as soon as the gateway is on:

  1. RS Pi 3 ON
  2. ./reset_lgw.sh start
  3. ./reset_lgw.sh stop
  4. leave for 1 minute
  5. Try $ ./util_tx_test -f 868 -r 1257
  6. If ok, Then try
  7. $ ./poly_pkt_fwd
  8. Is that process right.

What are the To-Do if Concentrator doesn't starts "ERROR: [main] failed to start the concentrator"

Timing synch accuracy and dev board access?

HI Matthieu, I stumbled across this project and I wonder if you could tell me more about it? Specifically, I'm wondering when the dev board for the 1301 that you're using (or are you primarily targeting the kerlink module?) will be available to users outside Semtech? Also, I see that you've added GPS synchronization to the code; what is the absolute time-resolution of the received time-stamps (the time-stamp of a received message from a remote LoRa wireless node)?

Cool project! Thanks - Rob

FPGA hex format

I am trying to flash the FPGA using the SEGGER JFlashSPI utility, but it seems to want a binary image.

I see that the FPGA images are now in a .hex format. What type of hex format is this? Intel, Motorola, Extended Tektronix hex?
Can I simply build a binary image composed of the bytes spelled out in the hex file?

Thanks,

Craig

lgw_receive assigning rxpkt.rf_chain and .freq_hz based on old if_chain

in lgw_receive function (loragw_hal.c) the lines:
p->rf_chain = (uint8_t)if_rf_chain[p->if_chain];
p->freq_hz = (uint32_t)((int32_t)rf_rx_freq[p->rf_chain] + if_freq[p->if_chain]);
use the rxpkt's if_chain to assign rf_chain and freq_hz, however the rxpkt's if_chain is not updated with p->if_chain = buff[sz+0]; until after these assignments are processed, so the rxpkt gets the previous packet's rf_chain and freq_hz values assigned to it.

just moving p->if_chain = buff[sz+0]; to above those assignments seems to fix.

Single-channel gateway

Hi,

I want to adapt library to work in Single-channel gateway mode. It is necessary to collect a cheap gateway based on SX127X modules for testing and debugging. Is it even possible to do this on the library by deleting a number of functions in loragw_hal and loragw_reg or easier to write such a library from scratch?

Thanks!

Problems with SX1301

I use Raspberry Pi 3 with RH0M301 (from RisingHF) to make a LoRa gateway with code from:
https://github.com/Lora-net/lora_gateway
And my end devices is made by RF95 and a microcontroller.

I try util_pkt_logger to receive packet from my end devices (without LoRaMAC), with config parameter from here: https://github.com/TheThingsNetwork/gateway-conf/blob/master/AS2-global_conf.json

I found out that sometimes my gateway receive a packet from unknown device, not from my end devices. I tested that my end devices can communicate with each other.

Can anyone tell me what is missing here? What are the requirements which both gateway and device have to follow to send or receive packet?
Thank you in advance!

Multi-receive on CN470 Band

Hi all,
Did some one test this code on CN470 Band before?
There is a strong things from my test, your can see my log below.

lgw_receive:1120: FIFO content: 3 60 0 7 19
lgw_receive:1139: [0 17]
Note: LoRa packet
lgw_receive:1120: FIFO content: 2 89 0 5 19
lgw_receive:1139: [6 17]
Note: LoRa packet
lgw_receive:1120: FIFO content: 1 b2 0 5 19
lgw_receive:1139: [7 17]
Note: LoRa packet

INFO: Received pkt from mote: 0603F073 (fcnt=0)

INFO: Received pkt from mote: 0603F073 (fcnt=0)

JSON up: {"rxpk":[{"tmst":20893108,"chan":6,"rfch":0,"freq":475.900000,"stat":1,"modu":"LORA","datr":"SF12BW125","codr":"4/5","lsnr":-12.0,"rssi":-64,"size":25,"data":"gHPwAwaAAAACQArgE/88ZErlDBWapnChrA=="},{"tmst":20893108,"chan":7,"rfch":0,"freq":476.100000,"stat":1,"modu":"LORA","datr":"SF12BW125","codr":"4/5","lsnr":10.2,"rssi":-13,"size":25,"data":"gHPwAwaAAAACQArgE/88ZErlDBWapnChrA=="}]}
INFO: [up] PUSH_ACK received in 0 ms
INFO: [down] PULL_RESP received - token[0:0] :)

This fcnt 0 packet has been received twice(maybe three, first is CRC bad). But actually it only send one time, and at 476.1Mhz. Why it also receive at 475.9Mhz? Is there interference? Or maybe I make some mistake on config file?

rxpk[0].time not chronological

I have iC880A connected to my device. I am running packet-forwarder on it. I have an external GPS connected via usb to my device and I have added "gps_tty_path" to local_conf.json. Packet-forwarder correctly connects to GPS device. However the GPS PPS signal is not conected to iC880A. Machine time is synchronized with GPS time, GPS has fix. My timezone is UTC+1.
The problem i have, is that packets received by packet-forwarder have wrong rxpk[0].time value, usually many seconds in the future and those values are not in chronological order.
Here are example of my logs:

Jan 26 19:34:28 JSON up: {"rxpk":[{"tmst":2775041860,"time":"2017-01-26T18:35:25.023600Z","chan":0,"rfch":1,"freq":868.100000,"stat":1,"modu":"LORA","datr":"SF9BW125","codr":"4/5","lsnr":-0.8,"rssi":-115,"size":14,"data":"XXXXXX="}]}
Jan 26 19:34:28 INFO: [up] PUSH_ACK received in 102 ms
Jan 26 19:34:30 INFO: [down] PULL_ACK received in 110 ms
Jan 26 19:34:31 
Jan 26 19:34:31 ##### 2017-01-26 18:34:31 GMT #####
Jan 26 19:34:31 ### [UPSTREAM] ###
Jan 26 19:34:31 # RF packets received by concentrator: 6
Jan 26 19:34:31 # CRC_OK: 100.00%, CRC_FAIL: 0.00%, NO_CRC: 0.00%
Jan 26 19:34:31 # RF packets forwarded: 6 (106 bytes)
Jan 26 19:34:31 # PUSH_DATA datagrams sent: 7 (1580 bytes)
Jan 26 19:34:31 # PUSH_DATA acknowledged: 85.71%
Jan 26 19:34:31 ### [DOWNSTREAM] ###
Jan 26 19:34:31 # PULL_DATA sent: 3 (100.00% acknowledged)
Jan 26 19:34:31 # PULL_RESP(onse) datagrams received: 0 (0 bytes)
Jan 26 19:34:31 # RF packets sent to concentrator: 0 (0 bytes)
Jan 26 19:34:31 # TX errors: 0
Jan 26 19:34:31 # BEACON queued: 0
Jan 26 19:34:31 # BEACON sent so far: 0
Jan 26 19:34:31 # BEACON rejected: 0
Jan 26 19:34:31 ### [JIT] ###
Jan 26 19:34:31 src/jitqueue.c:511:jit_print_queue(): INFO: [jit] queue is empty
Jan 26 19:34:31 ### [GPS] ###
Jan 26 19:34:31 # Valid time reference (age: 0 sec)
Jan 26 19:34:31 # GPS coordinates: latitude XXXXXX, longitude XXXXXX, altitude 95 m
Jan 26 19:34:31 ##### END #####
Jan 26 19:34:31 
Jan 26 19:34:31 JSON up: {"stat":{"time":"2017-01-26 18:34:31 GMT","lati":XXXXXX,"long":XXXXXX,"alti":95,"rxnb":6,"rxok":6,"rxfw":6,"ackr":85.7,"dwnb":0,"txnb":0}}
Jan 26 19:34:31 
Jan 26 19:34:31 INFO: Disabling GPS mode for concentrator's counter...
Jan 26 19:34:31 INFO: host/sx1301 time offset=(1485452893s:325012<C2><B5>s) - drift=60<C2><B5>s
Jan 26 19:34:31 INFO: Enabling GPS mode for concentrator's counter.
Jan 26 19:34:31 
Jan 26 19:34:31 INFO: [up] PUSH_ACK received in 63 ms
Jan 26 19:34:31 
Jan 26 19:34:31 INFO: Received pkt from mote: XXXXXX (fcnt=643)
Jan 26 19:34:31 
Jan 26 19:34:31 JSON up: {"rxpk":[{"tmst":2778433348,"time":"2017-01-26T18:35:31.415089Z","chan":2,"rfch":1,"freq":868.500000,"stat":1,"modu":"LORA","datr":"SF9BW125","codr":"4/5","lsnr":3.8,"rssi":-115,"size":19,"data":"XXXXXX=="}]}
Jan 26 19:34:31 INFO: [up] PUSH_ACK received in 79 ms
Jan 26 19:34:33 
Jan 26 19:34:33 INFO: Received pkt from mote: XXXXXX  (fcnt=418)
Jan 26 19:34:33 
Jan 26 19:34:33 JSON up: {"rxpk":[{"tmst":2780060292,"time":"2017-01-26T18:34:35.041228Z","chan":4,"rfch":0,"freq":867.300000,"stat":1,"modu":"LORA","datr":"SF9BW125","codr":"4/5","lsnr":1.0,"rssi":-119,"size":19,"data":"XXXXXX=="}]}

Packet received on 19:34:28 has "time":"2017-01-26T18:35:25.023600Z", that is 57 seconds in the future.
Packet received on 19:34:33 has "time":"2017-01-26T18:34:35.041228Z", that is only 2 seconds in the future, and the value is before "2017-01-26T18:35:25.023600Z".
The second packet was received (and sended) AFTER the first one, but the "time" field in jsons are not chronological (and are in the future).
I discovered that this "time difference" lowers whenever the loop in thread_timersync() runs.
Will connecting PPS signal to iC880A fix the issue?

serial for gps should be disabled the echo function

Hi
As I am working on the beacon function for class B, I connect the my Raspberry Pi B+ and ic880A with the GPS moudule (neo-6m-0-001).

Then I found many useless information like

$GPTXT,01,01,01,NMEA unknown msg*58
...

After connecting the uart_tx pin of rpi to my pc, I found it echo what it receive to the pc. That is the reason the GPS kept sending the warning message. Thus I add some code to the loragw_gps.c to disable the echo function.

int lgw_gps_enable() {
    ...
    ttyopt.c_lflag &= ~ECHO; // before tcsetattr()
    ...
}

Anyone has the same issues??

Version of calibration firmware not expected, actual:8 expected:2

I am trying to set up a Lora Gateway based on an iC880A-SPI board and a Raspberry Pi following the instructions of the iC880A-SPI_QuickStartGuide.pdf document. I have set up everything and successfully compiled the latest code (v3.2.0)
However I was not able to pass the test_loragw_reg test just like it was written in #10. After I changed the k.cs_change parameter to 0 like it was written there, the test seems to run successfully.

However I still cannot start the concentrator. The error I receive is the following:

lgw_spi_rb:371: BURST READ: to trans 8192 # chunk 1024 # transferred 1024
lgw_spi_rb:371: BURST READ: to trans 7168 # chunk 1024 # transferred 2048
lgw_spi_rb:371: BURST READ: to trans 6144 # chunk 1024 # transferred 3072
lgw_spi_rb:371: BURST READ: to trans 5120 # chunk 1024 # transferred 4096
lgw_spi_rb:371: BURST READ: to trans 4096 # chunk 1024 # transferred 5120
lgw_spi_rb:371: BURST READ: to trans 3072 # chunk 1024 # transferred 6144
lgw_spi_rb:371: BURST READ: to trans 2048 # chunk 1024 # transferred 7168
lgw_spi_rb:371: BURST READ: to trans 1024 # chunk 1024 # transferred 8192
Note: SPI burst read success
ERROR: Failed to load fw 1
Note: SPI read success
Note: SPI write success
Note: SPI write success
Note: SPI read success
Note: SPI write success
Note: SPI write success
Note: SPI write success
Note: SPI read success
ERROR: Version of calibration firmware not expected, actual:8 expected:2
ERROR: failed to start the concentrator

Can anyone advise how I can proceed from here?

Thanks:
Norbert

util_pkt_logger: ERROR failed to load fw 1?

I'm using Raspberry Pi 3, RHF0M301 - 915 to make a gateway. I ran util_pkt_logger and got this:

ERROR: failed to load fw 1
ERROR: Version of calibration firmware not expected, actual:0 expected:2

Can anyone please check and help me? I am new to github.

Failed in test_loragw_reg test, anyone can help?

My hardware are ic880a and raspberry pi, They are connected through SPI. I modify the lastest code a little(add the reset pin control). I tested the SPI write function with the logic analysor, it works well. But it can't pass the test_loragw_reg test, in which some read back values are fault.

Beginning of test for loragw_reg.c
Note: SPI port opened and configured ok
Note: Reset pin toggle ok
Note: SPI read success
INFO: no FPGA detected
Note: SPI read success
Note: SPI write success
Note: success connecting the concentrator
Note: SPI write success
Start of register verification
Note: SPI read success
###MISMATCH### reg number 0 read: 2 (2) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 1 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 2 read: 187 (bb) default: 103 (67)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 3 read: 45404 (b15c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 4 read: 32 (20) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 5 read: 163 (a3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 6 read: 126 (7e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 7 read: 169 (a9) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 8 read: 176 (b0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 9 read: 164 (a4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 10 read: 115 (73) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 11 read: 83 (53) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 12 read: 6084 (17c4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 13 read: 127 (7f) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 14 read: 66 (42) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 15 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 16 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 17 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 18 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 19 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 20 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 21 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 22 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 23 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 24 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 25 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 26 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 27 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 28 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 29 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 30 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 31 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 32 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 33 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 34 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 35 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 36 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 37 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 38 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 39 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 40 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 41 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 42 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 43 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 44 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 45 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 46 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 47 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 48 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 49 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 50 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 51 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 52 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 53 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 54 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 55 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 56 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 57 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 58 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 59 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 60 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 61 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 62 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 63 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 64 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 65 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 66 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 67 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 68 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 69 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 70 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 71 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 72 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 73 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 74 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 75 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 76 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 77 read: 3 (3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 78 read: 11 (b) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 79 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 80 read: 70 (46) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 81 read: 32 (20) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 82 read: 213 (d5) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 83 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 84 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 85 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 86 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 87 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 88 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 89 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 90 read: 5 (5) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 91 read: 50 (32) default: 240 (f0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 92 read: 747 (2eb) default: -384 (fffffe80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 93 read: 1320 (528) default: -128 (ffffff80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 94 read: -2395 (fffff6a5) default: 128 (80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 95 read: 622 (26e) default: 384 (180)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 96 read: -958 (fffffc42) default: -384 (fffffe80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 97 read: 304 (130) default: -128 (ffffff80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 98 read: 3313 (cf1) default: 128 (80)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 99 read: -503 (fffffe09) default: 384 (180)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 100 read: 3207 (c87) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 101 read: -1634 (fffff99e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 102 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 103 read: 4 (4) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 104 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 105 read: 55 (37) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 106 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 107 read: 125 (7d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 108 read: 49 (31) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 109 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 110 read: 18 (12) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 111 read: 121 (79) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 112 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 113 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 114 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 115 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 116 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 117 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 118 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 119 read: 6 (6) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 120 read: 13 (d) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 121 read: 10 (a) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 122 read: 6 (6) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 123 read: 0 (0) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 124 read: 14 (e) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 125 read: 11 (b) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 126 read: 0 (0) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 127 read: 2 (2) default: 5 (5)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 128 read: 21184 (52c0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 129 read: 49752 (c258) default: 4092 (ffc)
Note: SPI read success
###MISMATCH### reg number 130 read: 224 (e0) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 131 read: 211 (d3) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 132 read: 64 (40) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 133 read: 9 (9) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 134 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 135 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 136 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 137 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 138 read: 186 (ba) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 139 read: 78 (4e) default: 29 (1d)
Note: SPI read success
###MISMATCH### reg number 140 read: 3 (3) default: 9 (9)
Note: SPI read success
###MISMATCH### reg number 141 read: 3 (3) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 142 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 143 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 144 read: 10 (a) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 145 read: 6 (6) default: 2 (2)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 146 read: 55823 (da0f) default: 10 (a)
Note: SPI read success
###MISMATCH### reg number 147 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 148 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 149 read: 5 (5) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 150 read: 1 (1) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 151 read: 100 (64) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 152 read: 61 (3d) default: 255 (ff)
Note: SPI read success
###MISMATCH### reg number 153 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 154 read: 118 (76) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 155 read: 9 (9) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 156 read: 10 (a) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 157 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 158 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 159 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 160 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 161 read: 0 (0) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 162 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 163 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 164 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 165 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 166 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 167 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 168 read: 142 (8e) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 169 read: 251 (fb) default: 32 (20)
Note: SPI read success
###MISMATCH### reg number 170 read: 141 (8d) default: 100 (64)
Note: SPI read success
###MISMATCH### reg number 171 read: 42 (2a) default: 100 (64)
Note: SPI read success
###MISMATCH### reg number 172 read: 3 (3) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 173 read: 11 (b) default: 5 (5)
Note: SPI read success
###MISMATCH### reg number 174 read: 10 (a) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 175 read: 53 (35) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 176 read: 46 (2e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 177 read: 32 (20) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 178 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 179 read: 50 (32) default: 0 (0)
Note: SPI write success
Note: SPI read success
+++MATCH+++ reg number 180 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 181 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 182 read: 0 (0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 183 read: 12407 (3077) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 184 read: 9 (9) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 185 read: 0 (0) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 186 read: 7 (7) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 187 read: 88 (58) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 188 read: 100 (64) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 189 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 190 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 191 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 192 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 193 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 194 read: 1 (1) default: 5 (5)
Note: SPI read success
###MISMATCH### reg number 195 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 196 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 197 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 198 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 199 read: 4 (4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 200 read: 178 (b2) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 201 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 202 read: 5 (5) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 203 read: 10 (a) default: 2 (2)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 204 read: 6370 (18e2) default: 10 (a)
Note: SPI read success
+++MATCH+++ reg number 205 read: 1 (1) default: 1 (1)
Note: SPI read success
+++MATCH+++ reg number 206 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 207 read: 26 (1a) default: 10 (a)
Note: SPI read success
###MISMATCH### reg number 208 read: 2 (2) default: 3 (3)
Note: SPI read success
###MISMATCH### reg number 209 read: 115 (73) default: 29 (1d)
Note: SPI read success
###MISMATCH### reg number 210 read: 16 (10) default: 36 (24)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 211 read: 10774 (2a16) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 212 read: 0 (0) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 213 read: 2 (2) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 214 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 215 read: 47 (2f) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 216 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 217 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 218 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 219 read: 15 (f) default: 8 (8)
Note: SPI read success
###MISMATCH### reg number 220 read: 2 (2) default: 3 (3)
Note: SPI read success
+++MATCH+++ reg number 221 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 222 read: 5 (5) default: 7 (7)
Note: SPI read success
###MISMATCH### reg number 223 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 224 read: 16 (10) default: 255 (ff)
Note: SPI read success
###MISMATCH### reg number 225 read: 97 (61) default: 128 (80)
Note: SPI read success
###MISMATCH### reg number 226 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 227 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 228 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 229 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 230 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 231 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 232 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 233 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 234 read: 16 (10) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 235 read: 1 (1) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 236 read: 4384 (1120) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 237 read: 2253873348 (865760c4) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 238 read: 3794790410 (e22fe80a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 239 read: 31 (1f) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 240 read: 0 (0) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 241 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 242 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 243 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 244 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 245 read: 37 (25) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 246 read: 228 (e4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 247 read: 0 (0) default: 1 (1)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 248 read: 14796 (39cc) default: 0 (0)
Note: SPI write success
Note: SPI read success
###MISMATCH### reg number 249 read: 40 (28) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 250 read: 126 (7e) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 251 read: 89 (59) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 252 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 253 read: 37 (25) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 254 read: 212 (d4) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 255 read: 192 (c0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 256 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 257 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 258 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 259 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 260 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 261 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 262 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 263 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 264 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 265 read: 15 (f) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 266 read: 9 (9) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 267 read: 4 (4) default: 2 (2)
Note: SPI read success
###MISMATCH### reg number 268 read: 8 (8) default: 4 (4)
Note: SPI read success
###MISMATCH### reg number 269 read: 28 (1c) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 270 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 271 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 272 read: 0 (0) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 273 read: 40994 (a022) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 274 read: 137 (89) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 275 read: 148 (94) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 276 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 277 read: 160 (a0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 278 read: 12 (c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 279 read: 34 (22) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 280 read: 187 (bb) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 281 read: 115 (73) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 282 read: 98 (62) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 283 read: 209 (d1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 284 read: 141 (8d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 285 read: 8 (8) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 286 read: 22 (16) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 287 read: 1332 (534) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 288 read: 39121 (98d1) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 4 # chunk 4 # transferred 4 
Note: SPI burst read success
###MISMATCH### reg number 289 read: 2241045333 (8593a355) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 290 read: 1 (1) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 291 read: 12 (c) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 292 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 293 read: 13 (d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 294 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 295 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 296 read: 2 (2) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 297 read: 13 (d) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 298 read: 3 (3) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 299 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 300 read: 5 (5) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 301 read: 208 (d0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 302 read: 199 (c7) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 303 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 304 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 305 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 306 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 307 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 308 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 309 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 310 read: 0 (0) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 311 read: 0 (0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 312 read: 97 (61) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 313 read: 108 (6c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 314 read: 44 (2c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 315 read: 56 (38) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 316 read: 1 (1) default: 0 (0)
Note: SPI read success
+++MATCH+++ reg number 317 read: 1 (1) default: 1 (1)
Note: SPI read success
###MISMATCH### reg number 318 read: -32 (ffffffe0) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 319 read: 24 (18) default: 0 (0)
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
###MISMATCH### reg number 320 read: 4715 (126b) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 321 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 322 read: 10 (a) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 323 read: 12 (c) default: 0 (0)
Note: SPI read success
###MISMATCH### reg number 324 read: 24 (18) default: 0 (0)
Note: SPI write success
Note: SPI read success
###MISMATCH### reg number 325 read: 72 (48) default: 0 (0)
End of register verification
Note: SPI write success
Note: SPI write success
Note: SPI read success
IMPLICIT_PAYLOAD_LENGHT = 144 (should be 197)
Note: SPI read success
Note: SPI write success
Note: SPI read success
FRAME_SYNCH_PEAK2_POS = 2 (should be 11)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
PREAMBLE_SYMB1_NB = 33272 (should be 49253)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 4410 (should be 3173)
lgw_spi_wb:321: BURST WRITE: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 2 # chunk 2 # transferred 2 
Note: SPI burst read success
IF_FREQ_1 = -1782 (should be -1947)
lgw_spi_wb:321: BURST WRITE: to trans 256 # chunk 256 # transferred 256 
Note: SPI burst write success
lgw_spi_rb:383: BURST READ: to trans 256 # chunk 256 # transferred 256 
Note: SPI burst read success
Note: SPI port closed
Note: success disconnecting the concentrator
End of test for loragw_reg.c

Aslo I can ensure that the interface is connected well,

thanks!

LoRa Gateway without GPS Signal Available

Hi,

For our gateway deployment, we have to deploy the gateways inside buildings were there is no guarantee of GPS signal. But the gateway has a connection to NTP server.

In this scenario, do I have to make any changes to current source code available ?
Will the gateway still work without able to get a proper GPS signal?

Regards,
Shankar

Raspberry Pi to ic880A-spi communication fail at 8Mhz

I am trying to communicate Raspberry Pi board to ic880A-spi over spi .At spi speed 1 MHz its working fine but at 8 MHz sometime its working or sometime not due to PLL lock lose

do {
if (cpt_attempts >= PLL_LOCK_MAX_ATTEMPTS) {
DEBUG_MSG("ERROR: FAIL TO LOCK PLL\n");
return -1;
}
sx125x_write(rf_chain, 0x00, 1); /* enable Xtal oscillator /
sx125x_write(rf_chain, 0x00, 3); /
Enable RX (PLL+FE) */
++cpt_attempts;
DEBUG_PRINTF("Note: SX125x #%d PLL start (attempt %d)\n", rf_chain, cpt_attempts);
wait_ms(1);
} while((sx125x_read(rf_chain, 0x11) & 0x02) == 0);
From these part of code it get return whenever "failed to start concentrator". Please suggest how to remove this error.

Fatal error: can't create obj/util_spectral_scan.o: No such file or directory

The latest version of the lora_gateway build failed. The reason of this error is there's no obj directory in the util_spectral_scan directory.

make[1]: Entering directory /tmp/lora_gateway-master/util_spectral_scan' gcc -c -O2 -Wall -Wextra -std=c99 -I inc -D DEBUG_SPI=0 -D DEBUG_REG=0 src/util_spectral_scan.c -o obj/util_spectral_scan.o Assembler messages: Fatal error: can't create obj/util_spectral_scan.o: No such file or directory make[1]: *** [obj/util_spectral_scan.o] Error 1 make[1]: Leaving directory/tmp/lora_gateway-master/util_spectral_scan'
make: *** [all] Error 2

Receive unfiltered LoRa Frames

Hi All,

I'm currently working on a projet where I have to receive LoRa frames on a gateway.

I'm facing a trouble receiving frame which come from other GW. I guess that the SX1301 is defaulty configured to filter on end-devices uplink messages.

Is it possible to bypass this filter (through SPI regs by example) in order to receive all kind of messages?

Thank you for your assistance.
Sincerely

FPGA not start!

I use raspberry pi and SX1301AP2-PCB_E336, I have use raspberry pi pins MOSI , MISO , SCLK , CE0 and CE1 . CE0 choice SX1301 , and CE1 choice FPGA. When I start getway and module,getway can receive Join request , but mudule cannot receive Join Accept. If I connect SPI error , or need updata SPI drive ?

SPI pins

Hi,

Thanks for you great work!

Thanks!

RF module sometimes shut down itself

I have some gateways, sometimes RF module can't receive message from node without any error raised. And if I restart the application or restart the RF module, it works fine again. I have RF modules from several manufacturer(including IMST) and many of them have the same problem. Have you ever saw this problem?

Proposed change to reset_lgw.sh to allow a different GPIO to be used.

Hi,

Below is a proposed change to the script reset_lgw.sh to allow the GPIO number to be passed on the command line as the second argument. If no second argument is supplied, the script continues to use GPIO7 to maintain backwards compatibility.

8,9c8,9
< # ./reset_lgw.sh stop

< # ./reset_lgw.sh start

./reset_lgw.sh stop []

./reset_lgw.sh start []

11,12c11,21
< # The reset pin of SX1301 is wired with RPi GPIO7

< IOT_SK_SX1301_RESET_PIN=7

Which GPIO is wired to the reset pin of the SX1301? By default it is

assumed the GPIO is 7

Note: Using /bin/sh so need to use = and not == when testing

if [ "$2" = "" ]; then
IOT_SK_SX1301_RESET_PIN=7
else
IOT_SK_SX1301_RESET_PIN=$2
fi

3.2.1 version spi native issue on Linux kernel 2.6.30

Hi All,
in a lgw_spi_w function (spi_native) are present the following settings:
k.speed_hz = SPI_SPEED and k.bits_per_word = 8

that kind of protocol is not supported in atmel_spi driver present in 2.6.30 linux kernel.

Speed and bits per word seams to be already programmed into lgw_spi_open function so is there any specific reason to set it also in lgw_spi_w function ?

thanks in advance
Regards
Fabio

LoRa Gateway for .NET

I'm researching and thinking about creating a .NET CoreCLR implementation of the LoRa gateway; does/has anyone any knowledge of any projects implementing a LoRA gateway using .NET CLR/CoreCLR.

The aim is to create a gateway that can run on Windows, Linux and OSX using the platform created by the CoreCLR/ASPNET teams.

loragw_radio: SX125x #0 PLL??

After reseting by ./reset_lgw.sh, I ran ./util_pkt_logger, and the code can only start the concentrator for 1 out of 5 or 6 times. I found that the problem is from line 460 in loragw_radio.c, where start and PLL lock.
image
Can anyone tell me what is this problem with PLL, because it always wrong and I can rarely start the concentrator.
Thank you in advance.

Suggestion to use 'configure' to configure whole project.

Hi All,
I was testing lora_gateway library these days, and i feel a little confused about the libary.cfg file. Can we rebuild the makefile structure to use .configure to configure all things, include the debug, spi, board, frequency ect.

In current version, if a user wants to build the lora_gateway library, one must edit the library.cfg thing before compilation.

If we use configure to do these things, then just one command to configure and then make.

Inconsistent 'TX imbalance' warning

The hardware in question is the iC880a-SPI concentrator controlled using the SPI interface of the Raspberry Pi 3 using the spi_bcm2835 module.

Upon calling lgw_start(), occasionally the debug information shows 'WARNING: problem in calibration of radio A for TX imbalance'.

This message is seemingly generated based on the state of an SX1301 register for which documentation is unavailable. Is this warning serious or can it be ignored?

Before accessing the SPI interface, the hardware has been reset.

The configuration settings for the RF chain are displayed as follows:

rf_chain 0 configuration; en:1 freq:868500000 rssi_offset:-169.000000 radio_type:2 tx_enable:1
rf_chain 1 configuration; en:1 freq:868500000 rssi_offset:-169.000000 radio_type:2 tx_enable:0

Additionally, the TX gain table has been configured with values obtained from the iC880a documentation.

The same message occasionally appears when running the 'util_tx_test' program.

QCA9531's GPIO bitbang problem for cs_change

I successfully connect the IMST's lora gateway board to MT7628 with native SPI.

However, when it comes to the QCA9531 which doesn't port native SPI pins, it didn't work.

I tried SPI-GPIO bitbang, and it works for the other devices. But when I use the lora gateway,the CS pin behaves really wired.

So I disabled cs_change then. It works!!

https://github.com/sheenhx/lora_gateway/commit/403f82099b04c4a5d286df5732d4ff2e01115df5

Is there anyone who can tell me why did this happen?

Environment: OpenWrt CC15.05 Kernel 3.18.27

Use interrupt mode

Hi,
possible change software (add #define ... to library.cfg for example) so i can use GPIO mode 2 and GPIO0 as "rx_buffer_not_empty" on PIN7 to implement interrupt mode on RPi ?

Thanks in advance
Mitek

reference design doc?

Hello,
I am wondering if there are some reference design documents for lora-gateway with sx1301?

Thanks!

util_tx_text

I am trying to test Util_tx_test present in the Lora net folder. Steps followed

  1. Compiled the Util_tx_test module and generated the executable.
  2. Run the program with frequency setting to 867.9 and radio type as 1257.
  3. Able to see the packet transmission successful but not able to receive it.
  4. Using GL6509 Low Power WAN module to receive the data. Able to receive the data packet by the util_pkt_logger sending by GL6509 though.

Please help me if i miss anything.

internet connection check

for the packet forwarder, how to include internet connection check and reconnect upon internet connection became alive.

Is hybrid mode included in this version?

Hi, recently your FAE Michael Fink told us that the hybrid mode is in this github. But we can't find it anywhere. Do you have plan to release it soon? Thanks!

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