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Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)

Makefile 0.38% Python 78.70% Verilog 9.83% VHDL 1.01% Shell 0.10% Tcl 0.13% TeX 0.04% Prolog 9.22% C 0.21% SourcePawn 0.01% Scala 0.01% SuperCollider 0.01% Lex 0.02% Yacc 0.04% Standard ML 0.01% Perl 0.27% Awk 0.04% C++ 0.01% Ruby 0.01%

vlsi-design

alliance-check-toolkit's Introduction

Alliance Check Toolkit: Tests and Benchmarks for Alliance and Coriolis

This repository contains examples, benchmarks and tests for the Coriolis VLSI toolchain and its older counterpart Alliance.

It contains all kinds of designs using Coriolis for physical design (typically placement and routing).

For any question, you may contact the team on Matrix.

Installation

You should clone the repository in ~/coriolis-2.x/src/, and install Coriolis and Alliance.

# Clone the repositories
mkdir -p ~/coriolis-2.x/src/
git clone https://github.com/lip6/coriolis.git
git clone https://github.com/lip6/alliance.git
git clone https://github.com/lip6/alliance-check-toolkit.git

# Install Alliance and Coriolis
cd coriolis
bootstrap/allianceInstaller.sh
make install

Example design

As an example, you can look at the Arlet6502 design in benchs/arlet6502/cmos. It uses pydoit to define build steps in dodo.py.

You can build it with:

# Source Coriolis (adapt to your build path)
eval `~/coriolis-2.x/Linux.x86_64/Release.Shared/install/etc/coriolis2/coriolisEnv.py`

cd benchs/arlet6502/cmos
# Cleaning step
doit clean_flow
# Run each step individually
doit yosys
doit pnr
# You can just run this one, as it depends on the others
doit lvx

It's often nicer to use the viewer and see your design:

doit cgt
# Go to Tools->Python Script
# Write "doDesign"
# Enjoy

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alliance-check-toolkit's Issues

Change transistor model names in GF180mcu DKS

Change Skywater 130 DRC file from laurentc2 to https://github.com/klayoutmatthias/sky130A_el

The DRC deck from laurentc2 has some errors.
We should use Matthias's drc file instead.

8080 adaptation for Coriolis and nsxlib2

Change setting files for Coriolis

remove unrelated file from 8080/sg13g2

nsxlib2/sff1r_x4 extend NITE

On some designs, NTIE did not connect between cells. So we have to extend it to the out of the border to connect with the next cell.

add sg13g2 and gf180mcu to 6502

RISC-V SG13G2 layout example

We cannot execute IHP's DRC deck in batch mode, therefore, you may have to run it with GUI.
With klayout DRC, there are many coverage errors.
Usually, these errors will be treated by the foundry or layout tools.
Then I left them untouched.

Clashing file names on non-case-sensitive filesystems (mac)

The following files clash on checkout on mac:

benchs/arlet6502/sky130_c4m/spi/Arlet6502.spi
benchs/arlet6502/sky130_c4m/spi/arlet6502.spi
benchs/arlet6502/sky130_c4m/spi/cmpt_ALU.spi
benchs/arlet6502/sky130_c4m/spi/cmpt_alu.spi

addition to #59

Patch a little more on techno.py and techno_symb.py.

add evaluation script for 8080

just add shell script for evaluation

Support Skywater130 with nsxlib2

Modify cells to support skywater130.
Original nsxlib2 uses symbolic distance for poly-cont, poly-poly as 2 lambda.
But skywater 130 requires 150 nm poly width and 250nm for poly-cont, 210m for poly-poly.
It may induce larger layout then I changed symbolic layout of nsxlib2 as poly-cont , poly-poly as 3 lambda.

Resolve unrouted vertical wire on RISC-V/Menerva/sky130_sym

change the core size to extend the vertical length.

nsxlib2 GF180mcu support

Provide the design kit for GF180mcu for nsxlib2.
This design does not have the Deep NWELL and surrounding guard rings.
These are a waste of space if we have them on each cell.
Then chip designers should have their own DNWELL and guard rings before taping out.

nsxlib make check-lib failed

some cells had DRC errors.

add CATAL in nsxlib2

nsxlib2 skywater adaptation

change some cells and rds

GF180mcu for nsxlib2 update

remove unsupported feature in background for sg13g2 drc

add RISC-V sample for GF180mcu layout

IHP SG13G2 suport on nsxilb2

Add an RDS file for the sg13g2 and slightly tuned layout of a4_x2 and sff1r_x4.
Since the ACTIVE rule the ACT.b is not cleared with the original layouts, I had to change them.

This implementation requires the latest Alliance version to designate the physical grid as 0.001.

Add pin layer flag to 8080 ihp example

small test case on benches/adder

For investigating skywater symbolic layout, I added a small example.

sky130_nsx3.rds modify for p&r

The turn via layer was not properly defined.
Also the implants for body contact was missing.

GF180mcu add another example

remove obsolete files for nsxlib2

Revert commit failuer

Add pin layer sample to 8080 skywater, separete the setup for Skywater130 techs from Coriolis source code

Add IHP SG13G2 gds example

Add an example to generate the gds file from symbolic nsxlib2.

pin layer added to RDS on skywater130 and sg13g2

i8080A compatible CPU for symbolic layout test

Only the core of Midway,I extracted i8080A compatible CPU core to test the skywater 130 symbolic layout.
It uses nsxlib2 for synthesizing the CPU with sff1r_x4 which is flip-flop with reset.

bench/8080 layout generation for sky130 symbolic

modify for required changes.

GF180mcu guard ring and deep nwell support

set overlap value to big vias on GF180mcu

Add dsk based skywater 130 symbolic layout example on Minerva RISC-V

delete zero length segment on nmx3_x1 in nsxlib2

Unexpected CALU1 segment exist on nmx3_x1

sg13g2.rd shrink m1, set sheet resistance

Adapt dks to sg13g2

I copied most files from sky130_nsx2.
Now I changed the parameters in sg13g2_nsx2 to adapt for the value in sg13g2.

add Alliance layout generation on benchs/adder/sky130_sym

to compare with Coriolis layout, I added Alliance Makefile

make -f Makefile.alliance clean all

will generate the symbolic layout with Alliance.

Add asyncronous reset design in 6502

Remove zero length segments in nsxlib2

We had two cells that contained zero-length segments.

mx3_x2
sff1r_x4

Remove these segments.

Turn off density rules on IHP SG13G2

nsxlib2 skywater130 RDS

You need '8-gds-datatype-support' version of Alliance to generate GDS compatible with Skywater130.

Symbolic layout support for Minerva RISC-V

add new directory on bench/RISC-V/Minerva

Modify dodo.py to use alternative DRC file in 8080, adder and RISC-V/Minerva

As the title, we changed the DRC file to the one from Matthias.

ANanlog Pareto Front

I launched the layout generation in benchs/analog
Ota/350 or gmChamla
in both cases I ask to update possible dimensions,
in both cases I see the SlicingTree's Pareto front,
the different sizes are also displayed in the Slicing Tree's possible dimension window,
if I click on one instance, the new placement is displayed in cgt,
BUT if I click on one point of the Slicing Tree's Pareto window, nothing is done.
Could you please fix this issue?
Thanks!

remove nolonger needed rds file

missing lynx_graphs parameters on nsxlib2 RDS tables

On sky130_nsx3.rds and sg13g2.rds, I found that there is some missing parameters.