Import/Export to Verilog/VHDL about logisim HOT 14 OPEN

Other options: http://www.verilog.com/VerilogBNF.html
Parsing via JParsec

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This would be very cool! AWESOME IDEA ! +1 😸

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Brilliant idea! Any progress?

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Any progress on this idea.

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No :(

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The Logisim-evolution fork does offer to export structural Verilog and VHDL models as part of its FPGA Commander module. The generated HDL code is placed in a directory under the Logisim-evolution workspace. The FPGA Commander automates the whole logic synthesis and design download flow to an extensible list of CPLD and FPGA evaluation boards. VHDL entities can be integrated into Logisim schematics and the resulting designs can be simulated with a third-party commercial HDL simulator.

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That third-party commercial HDL simulator is an annoyance - it makes VHDL entities almost useless for people wanting to simulate them without needing paying a license for this simulator. :(

I wonder if PSHDL (http://pshdl.org/) can be integrated with logsim. Source can be found in https://bitbucket.org/kbecker/profile/repositories and appears to be Java.

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You can test my logisim-evolution fork with ghdl support
https://github.com/roy77/logisim-evolution

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Is this idea still in work in progress? I would love to contribute to this. Any hints on how I should proceed? Thanks a lot.

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The implementation of ghdl works. My tests were successful. You can test it, maybe you find a bug. I replaced the Questa Advanced simulator with Ghdl. Before it will be pulled to logisim-evolution I have to re-implement Questa Advanced simulator. You can fork my repository, re-implement Questa Advanced simulator and request a pull from logisim-evolution. The earliest possible date I can resume my work is in june.

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Is there a compiled jar available for your forked logisim-evolution that uses GHDL in place of Questa?

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logisim-heintz.zip

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I have made a similar tool that uses Yosys to create entities/components from verilog code.

Try it out at, digsim and feel free to copy the concept if you like it.

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Try this version of Logisim, It can export to Verilog

Link: https://github.com/hneemann/Digital

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