While I can largely figure this out from the example schematics. It is not clear from looking at the pinout.

From looking at both carrier schematics REFCLK3 seems to belong to HSIO 1 and 3?

Hi,

we just design our product using your module, so:

• what about PCIe BIOS? We prefer maximum number of PCI and 2 or 4 USB 3. What is a planed configuration for that bios?
• We strongly prefer using only DP/eDP ports. There is any possibility to use all TCP ports for DP? According ADL-N datasheet, it should be possible....

Thanks.

Hi! How can i get bios config with next ports?

HSIO0: USB 3.2 10Gbps
HSIO1: PCIe 3.0 x1
HSIO2: PCIe 3.0 x1
HSIO3: PCIe 3.0 x1
==========
HSIO8: SATA 3.0
HSIO9: SATA 3.0
HSIO10: SATA 3.0
HSIO11: SATA 3.0
==========
HSIO6: PCIe 3.0 x1

And, if possible, status leds for each sata

I would like to use the TCP0 and TCP1 as Type-C with alt-mode. Diagram of what I am trying to do:

From what I can tell, these will require a PD controller. The full carrier board schematic uses a IT8851:

However I am unable to acquire an IT8851. I will use an MCU and control power delivery from that.

From what I can tell in the N100 datasheet, 26.1.1 states the following:

SMLink1 is used to communicate with USB-C* PD Controller on the platform to
configure different modes such as USB, Display Port, Thunderbolt*, etc. When used
for Integrated USB-C purposes, a soft strap must be set to indicate that integrated
USB-C ports from CPU are being used.

26.2 (yes wrong image, see comments below for right one)

This matches with what I see in the schematic for pins 3, 4 and 5. The datasheet also mentions a second I2C port (I2C2 on the module), something with retimers.

Although beyond what the datasheet states, there is nothing describing what messages get sent to and from the PD controller.

Regarding the I2C/Smbus interface, is this defined by the SoC or defined by the BIOS? Is LattePanda able to describe the interface to configure the USB-C port mode and muxing in TCP0 and TCP1 over smbus (what messages, layout of each message)? How many I2C interfaces do I need to use for this (1 or 2)?

I tried to see if coreboot had anything to reference on this. I could not find anything.

The Mu docs lists both Ubuntu 22.04 (with HWE kernel) and Ubuntu 24.04 in the Official Support list but only lists Ubuntu 22.04.2 as having been tested / in the "Compatible list"

1. Could you clarify whether the Mu is compatible with 24.04 ?
2. What is the consequence of not installing the HWE Kernel on 22.04? Also, the 24.04 has no HWE kernel yet, what's the consequence of that on using the Mu?

Thank you very much for adding the documentation about the pinouts.

It would be nice if you could also add a column in the pinout table of the SODIMM pinout that documents the voltage level of each pin.

For example UART0_RXD and UART0_TXD - are they 3.3V CMOS or 1.8V? The same for SLS_S0 / SLS_S3, the GPIO, the SPI, the I2C buses.

The schematics for the Full EVA Carrier has a note that some voltage levels can be changed. If I understood this correctly, this is probably done together for several IOs that are on one voltage rail. Then please document which pins are together on one voltage rail and what is the default voltage level.

Regarding the TSENSE pin: this is probably a NTC that has 10 kOhms at 25°C. Could you please document which beta value to use for proper temperature readout?

Would you please add TGPIO enablement support to the BIOS.
TPGIO is available on APTIO as an optional feature.

What is the power input of the full carrier? Will you opensource ur bios?