A simple single-cycle 16-bit processor designed for educational purposes. Written in VHDL.

For the simulation process, the supported method is to use Parvaj (which makes use of GHDL and GtkWave). You can also use well-known possibly-commercial tools (like Xilinx ISE), but you're completely on your own.

First, clone the project with all its dependencies:

git clone https://github.com/Kiarash-Parvizi/ZINQ-Processor --recursive

Now, you need to initialize Parvaj. Install the requirements specified here, and then do the following:

composer install -d scripts/parvaj/

Everything is ready. Deep dive into simulating the project:

./scripts/parvaj/bin/parvaj simulate test_main --waveform=vcd

Note: This could take a while (about 2 minutes on my personal system).

Boom! You can now see a simulation of the processor. Dig into the source code and learn more!

Almost all entities are well-tested and for each, a unit-test (i.e. test-bench) is written. Feel free to simulate those tests as well.

For instance, if you want to test the controller alone, run:

./scripts/parvaj/bin/parvaj simulate test_controller

Note: The process should work on all Linux distributions, and other Unix variants. Windows users might be able to simulate as well, however it's not guaranteed.

Note: If the simulation process takes forever, you should either use --stop-time=1ns (prevent to run infinitely), or --waveform=vcd. In latter case, the reason is sometimes the default GHW waveform output format causes GHDL to hang.

Every processor has an instruction set and instructions format (defined as layout of bits of instructions). These two defines what the processor features and how it can be used (e.g. by a compiler). However, these are only definitions, and they have to be actually implemented.

In a simple realization, ZINQ processor divides into two separated but connected datapath and controller entities. They are first designed conceptually and visually, and then implemented in VHDL, making the design process simple.

In the datapath, we have two register files named as Main and Bank. The main has 8 registers and the bank has 4.

Keep going for more details.

ZINQ processor has four types of instructions, Z-type, I-type, N-type and Q-type. Each type has a unique format shown in the table below.

• OPC and Funct: Operation of the instruction. Specifies which instruction is it, along with its type (e.g. Z-type) to extract other fields.

• R* and Addr: The number of a register, in which its value is used when referenced. The first one is for the main register file, the second is for the bank one.

• Imm*: A constant value. Stands for immediate.

• Shamt: Shift amount used in dynamic shift operations.

For more details, see the Instruction Set section below.

• S.E: Sign Extend
• Z.E: Zero Extend
• U.S: Unsigned
• &: Concatenation
• <<: Left Shift
• ^: Power (i.e. Exponentiation)

The controller is an FSM (Final State Machine).

If you want to know how the connection signals between datapath and controller are implemented and optimized, see this image.

Feel free to contribute of any kind. By any kind, we mean just ANY kind! :)

The code is well-documented, and this README should help you through the general overview of the project.

But you think it is a must? Create an issue and tell why.

Licensed under GPLv3.